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ap01
一個紅外線感測電路的設計,是經由opa來設計。(An infrared sensing circuit design, is designed by opa.)
- 2011-10-19 14:22:24下载
- 积分:1
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基于FPGA可触控卫星信道模拟器的设计与实现
卫星信道模拟器能够模拟卫星信道的传播特性,用于设备的通信调试,节
约研发成本。目前,很多卫星信道模拟器在参数设置上存在问题:有的参数难
以调节;有的采用上位机进行参数设置,通过上位机设置参数需要连接电脑,
适应性差。针对上述问题提出了一种基于FPGA可触控卫星信道模拟器,FPGA
作为算法实现和控制单元,通过控制触摸屏方便快捷的实现参数设置。(Literature of Satellite Channel Simulation Based on FPGA)
- 2020-12-10 20:59:20下载
- 积分:1
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GW48系统电子琴:可控制8个音节,4种音调 readme中带使用说明
GW48系统电子琴:可控制8个音节,4种音调 readme中带使用说明-GW48 system : control eight syllables, four species of taking the pitch readme use
- 2022-05-21 12:22:34下载
- 积分:1
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05_fifo_test
说明: FIFO: First in, First out 代表先进的数据先出,后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO,根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)
- 2021-04-08 22:19:20下载
- 积分:1
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计时器程序设计
利用Quartus 综合简单的计时器功能,欢迎大家下载、参考。谢谢大家的支持!
- 2023-05-24 21:20:03下载
- 积分:1
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formal_verification
说明: 现在最流行的RTL设计方法之一,本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)
- 2020-06-23 22:00:02下载
- 积分:1
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divider
verilog HDL编写的浮点除法器,编译通过,可综合。压缩包包含三个文件。(verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.)
- 2011-08-29 09:12:21下载
- 积分:1
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EDA
EDA-Verilog 编码原则,初学者必看!-EDA-Verilog coding principles, beginners must-see!
- 2022-02-20 01:38:26下载
- 积分:1
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16b20b_Encoder
16b20b encoder and decoder
- 2013-02-04 13:24:46下载
- 积分:1
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irig_b
用来实现IRIG_B码的解码程序,在XILINX ISE上运行过没有问题,(Used to achieve IRIG_B code decoding process, in XILINX ISE run-off is no problem,)
- 2021-04-06 14:49:03下载
- 积分:1