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tb_modular
Matlab to hdl code for Least_square testbench
- 2020-06-17 12:20:02下载
- 积分：1
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apb_uart_sv-pulpinov1
SystemVerilog 写的APB总线接口的uart 代码，带testbench.(Uart code of APB bus interface written by SystemVerilog, with testbench.)
- 2018-04-17 14:44:15下载
- 积分：1
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Fast_median_filter
说明： FPGA数字图像处理实现均值滤波，并且仿真将生成图片写出TXT格式以便使用MATLAB查看(Mean filter is realized by digital image processing in FPGA, and the generated image is written in TXT format for viewing with MATLAB.)
- 2019-06-01 21:23:25下载
- 积分：1
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USB_devide
利用最新的嵌入式开发工具EDK，在FPGA 中完成对PDIUSBD12 的硬件定制和固件编程，从而在FPGA
中实现U S B 控制器， 并最终完成U S B 的枚举过程、驱动程序的开发和简单的应用。(Using the latest embedded development tools, EDK, in the FPGA completes its PDIUSBD12 custom hardware and firmware programming, in order to realize USB controller in the FPGA, and ultimately complete the USB enumeration process of driver development and simple应用.)
- 2007-10-04 16:27:44下载
- 积分：1
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MAX2839 SPI寄存器
MAX2839寄存器配置 spi程序 &nbs
- 2022-08-25 09:05:38下载
- 积分：1
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lcd_system
LCD显示工程，其中包含了顶层文件和各个底层文件(LCD display project, which contains the top-level document and all underlying file)
- 2013-07-24 08:58:53下载
- 积分：1
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VHDL-Code-For-Full-Adder-By-Data-Flow-Modelling
VHDL Code For Full Adder By Data Flow Modelling
- 2013-11-08 00:39:04下载
- 积分：1
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MAX262
MAX262是一款可程控滤波芯片,该是它的英文数据手册.(MAX262 is a programmable filter chip, which is its data sheet in English.)
- 2007-08-14 16:32:01下载
- 积分：1
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Verilog_HDL时序篇 教程及代码
(A good set of learning information for Verilog timing chapter, with source code and engineering documents, you can follow the tutorial self-study)
- 2022-03-12 10:55:15下载
- 积分：1
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Desktop
说明： qpsk的fpga实现，包含调制和解调部分，使用verilog语言(FPGA implementation of QPSK)
- 2019-03-16 02:52:26下载
- 积分：1
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