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VHDL——如何写简单的testbench
基于VHDL的testbench编写攻略(VHDL based on the preparation of testbench Raiders)
- 2017-07-31 15:00:45下载
- 积分:1
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这是用Verilog HDL写的可调占空比分频控制器,可以挂在Avalon总线上使用...
这是用Verilog HDL写的可调占空比分频控制器,可以挂在Avalon总线上使用-This is written in Verilog HDL with adjustable duty cycle frequency controller, can be hung on the Avalon bus use
- 2022-09-09 08:45:02下载
- 积分:1
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全加器的VHDL程序实现及仿真
全加器的VHDL程序实现及仿真-full adder VHDL simulation program and
- 2022-02-03 16:51:49下载
- 积分:1
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microsemi
说明: microsemi的Libero IDE 软件内部IP核详解(Microsemi's Libero IDE software internal IP kernel details)
- 2021-03-31 10:09:09下载
- 积分:1
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四选一选择器,输入四个,输出1个.当NM=00时选A 当NM=01时选B 当NM=10时选C 当NM=11时选D...
四选一选择器,输入四个,输出1个.当NM=00时选A 当NM=01时选B 当NM=10时选C 当NM=11时选D-four elected a selector, the importation of four, Output 1. When NM = 00 A at the election when NM = 01 am when the election NM B = C 10:00 when the election NM = 11:00 election D
- 2023-04-13 16:10:03下载
- 积分:1
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dingshi
定时器加数码管显示源码,以及test bench测试模块源码,经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)
- 2013-07-27 10:34:41下载
- 积分:1
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The_entire_FPGA_design_flow_Modelsim_Synplify
详细的说明了FPGA设计的整个流程
FPGA设计全流程Modelsim>>Synplify.Pro>>ISE(Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE)
- 2009-04-06 10:12:48下载
- 积分:1
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使用vhdl语言实现对led的控制,还有电路仿真
使用vhdl语言实现对led的控制,还有电路仿真-Using vhdl language implementation of the led control, as well as circuit simulation
- 2022-03-12 11:40:55下载
- 积分:1
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TCD1304_drive
FPGA驱动TCD1304AP线阵CCD,并经采集将数据通过串口传输至上位机(FPGA drives TCD1304AP linear CCD, and by collecting the data transmitted through the first bit machine serial)
- 2021-05-15 18:30:02下载
- 积分:1
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sin and cos with cordic VHDL
该模块采用cordic算法计算正弦和余弦,并采用参数化方式实现。 ;包中存在其他模块。
- 2022-05-25 06:14:20下载
- 积分:1