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Verilog计数器、编码器、加法器
说明： verilog编码器、计数器、加法器的程序(Verilog encoder, counter, adder procedures)
- 2019-01-26 21:50:01下载
- 积分：1
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计数器 0 到 9999
本程序显示在 BCD display 数从 0 到 9999.This 程序进行了智能 2 FPGA 板。
- 2022-05-08 02:50:35下载
- 积分：1
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串口中断＿niosII.rar
解压密码：www.21control.com
串口中断＿niosII.rar
解压密码：www.21control.com
- 2023-01-05 21:10:04下载
- 积分：1
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can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do wit...
可YCrCb2RGB集成模块（Verilog）采用三行，它们简单的做分数运算，有流水线技术
- 2022-07-15 16:05:34下载
- 积分：1
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izhihuangenzongPWMnb
三相电流滞环跟踪PWM逆变器。逆变电路负载电流与指令电流比较产生PWM波形。经验证可很好实现功能。(The three-phase hysteresis current tracking PWM inverter. Load current command current of the inverter circuit generating a PWM waveform. Proven functions well.)
- 2012-11-26 11:56:56下载
- 积分：1
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HDMI接口编解码传输模块ASIC设计_刘文杰
说明： ? 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
? 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。
? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
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eDP
eDP接口TFT-LCD显示驱动原码（verilog+c）(eDP Interface TFT-LCD display driver source code (verilog+c))
- 2020-10-17 09:17:27下载
- 积分：1
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jiaotongdeng
Quartus2环境下基于VHDL状态机的交通灯程序(VHDL state machine traffic lights based on Quartus2 environment)
- 2014-01-13 21:57:00下载
- 积分：1
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大唐电信的FPGA设计经验，内部资料，详细完整，很有参考价值...
大唐电信的FPGA设计经验，内部资料，详细完整，很有参考价值-Datang Telecom
- 2022-03-04 13:47:05下载
- 积分：1
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FPGA_UART
用Verilog语言实现的FPGA UART独立收发模块
思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond.
功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。(Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.)
- 2011-10-03 13:18:56下载
- 积分：1
