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Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.
描述了使用FPGA接口PDIUSBD12开发USB接口的流程.-Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.
- 2023-04-29 07:25:03下载
- 积分：1
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Verilog 下脉冲发生器的源代码，可用于模拟三相交流电过零点，主要用于调试一些类似SVC（无功补偿）控制器的一些算法...
Verilog 下脉冲发生器的源代码，可用于模拟三相交流电过零点，主要用于调试一些类似SVC（无功补偿）控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) controller of a number of algorithms
- 2023-06-15 23:20:03下载
- 积分：1
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Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。...
Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis
- 2022-03-21 18:04:20下载
- 积分：1
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verilog 编写基于SRAM(CY7C1041)的代码
verilog 编写基于SRAM(CY7C1041)的代码-Verilog prepared based on the SRAM (CY7C1041) code
- 2022-07-05 00:16:39下载
- 积分：1
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CH4CH2CH1VHDL 数字电路参考书所有程序5
CH4CH2CH1VHDL 数字电路参考书所有程序5-CH4CH2CH1VHDL digital circuit reference all proceedings 5
- 2022-04-07 20:48:28下载
- 积分：1
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clock_seg
用FPGA分频，做一个有时分秒的时钟，并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)
- 2013-05-20 13:53:06下载
- 积分：1
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用Verilog 实现的电子时钟，给初学者一个模版，学习Verilog。
用Verilog 实现的电子时钟，给初学者一个模版，学习Verilog。-Using Verilog realize an electronic clock, a template for beginners to learn Verilog.
- 2022-03-01 20:04:47下载
- 积分：1
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fpga2
FPGA学习的非常好的资料，希望广大朋友都可以学习学习啊(FPGA to learn very good information, I hope our friends can learn ah)
- 2013-05-28 22:09:28下载
- 积分：1
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led5604
5604FPGA驱动，能显示数字（5604里面为4个595）(5604 FPGA driver, able to display digital (5604 contains 4 595))
- 2020-06-19 18:00:01下载
- 积分：1
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EMAC6
verilog实现的FPGA三态以太网链路层通信代码，里面有状态机，并按各个模块的功能分了文件夹，还有说明文档，自定义帧的产生和接收，开发环境为Xilinx ISE，测试无误。(verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well as documentation, self-defined frame generation and reception, the development environment for the Xilinx ISEtest and correct.)
- 2013-01-09 00:04:20下载
- 积分：1
