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FPGA实现UART接收和发送
在fpga中实现实现了UART的功能,经过实际在ep4cE6 fpga上下载测试,发现可以准确的接收个发送串口数据,和板子上的单片机uart通信正常。要使用的小伙伴,可以直接拷贝使用。
- 2022-01-31 07:33:26下载
- 积分:1
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ATAN_CORDIC
使用cordic算法,基于verilog实现的atan功能,经过仿真验证,适宜工程使用。(ATAN,implemented with cordic.)
- 2018-09-26 11:19:50下载
- 积分:1
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shiyan5
应用布莱克曼窗实现FIR滤波器,并绘制相应波形图案(Application Blackman window FIR filter, and draw the corresponding waveform pattern)
- 2014-01-09 11:50:49下载
- 积分:1
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802-11-Frame_E_C
Frame Control field
Retry:
Set in case of retransmission frame
More fragments:
Set when frame is followed by other fragment
Power Management
bit set when station go Power Save mode (PS)
More Data:
When set means that AP have more buffered data for a
station in Power Save mode
- 2016-08-23 17:37:40下载
- 积分:1
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water_light
Verilog语言的流水灯设计程序,对初学者很有用。(Water lights Verilog language design program useful for beginners.)
- 2015-03-15 13:48:43下载
- 积分:1
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data_swith
verilog 代码实现串并转换,有延迟(Verilog code and string conversion, delay)
- 2011-07-31 23:58:17下载
- 积分:1
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deng
HDL verilog 电子密码锁 输入错误后有报警 输入正确后有提示(HDL Verilog electronic code lock input errors have prompted alarm input is correct)
- 2012-06-27 19:25:53下载
- 积分:1
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tdma_code
tdma参数化模块。可以自动生成2的n次的tdma哥时隙,用户可根据需要自己配置参数(tdma see the number of model lumps. 2 n basis following manner tdma chance possible 以自 dynamic generation, for root needed self-placement see number)
- 2013-09-03 21:52:51下载
- 积分:1
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clock
软件开发环境:ISE 7.1i 仿真环境:ModelSim SE 6.0 1. 多功能数字钟(Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock)
- 2009-03-22 12:44:34下载
- 积分:1
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cic_compensating
CIC 补偿滤波器。采用两种方法来设计,一个是frequency sampling method。另一个是Equal Rippler Design Method。这是一个非常有用的matlab代码。(CIC compensation filter. Two ways to design a frequency sampling method. The other is an Equal Rippler Design Method. This is a very useful matlab code.)
- 2012-10-17 14:22:08下载
- 积分:1