登录
首页 » Verilog » Q8051

Q8051

于 2023-07-08 发布 文件大小:4.73 MB
0 89
下载积分: 2 下载次数: 1

代码说明:

Quick Cores 的Q8051,带JTAG接口,编译时提示调试模块缺少TRACE模块。

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • turbo_encoder
    在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。(Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.)
    2021-04-19 09:38:51下载
    积分:1
  • RS2
    该源代码是RS(31,19)码的完整编译码程序,采用的是VerilogHDL语言,包含了RS码的编码和译码,这蛋疼的东西花费好多时间(The source code is RS (31,19) code complete encoding and decoding procedures, and spend a lot of time using is VerilogHDL language contains the encoding and decoding of RS codes, this egg pain)
    2012-09-09 13:04:41下载
    积分:1
  • ddr2_controller
    A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.
    2015-11-16 00:31:22下载
    积分:1
  • traffic 2
    说明:  实现主干道交通灯显示,以状态机程序实现,并用数码管进行红绿灯倒计时的显示,内置计数模块,交通灯控制模块,数码管显示模块,并对各模块用电路图的方式进行连接。对于学习VHDL语言有所帮助。(The main road traffic light display is realized by the state machine program, and the digital tube is used to display the traffic light countdown. The counting module, the traffic light control module and the digital tube display module are built in, and each module is connected by the circuit diagram. It is helpful for learning VHDL.)
    2020-06-25 19:55:12下载
    积分:1
  • MifFileGen
    VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子,生成的是一个定点的正弦数据表文件,需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)
    2013-07-19 02:32:45下载
    积分:1
  • DLX-pipeline-in-verilog
    verilog实现DLX指令集5段流水线(5 stage DLX pipeline implemented in verilog)
    2013-08-24 22:59:48下载
    积分:1
  • CCD_Verilog_1014
    基于CPLD器件的线型CCD东芝TCD1501的驱动程序,用verilog语言开发。(CPLD devices based on linear CCD driver Toshiba TCD1501 using Verilog language development.)
    2016-04-24 12:52:19下载
    积分:1
  • FIR_poroje
    this project is about FIR FIlter By VHdl codes in the ISE.
    2013-09-29 19:25:16下载
    积分:1
  • 自适应fir滤波器verilog代码及仿真波形
    自适应滤波器是指利用前一时刻的结果,自动调节当前时刻的滤波器参数,以适应信号和噪声未知或随机变化的特性,得到有效的输出,本设计在MATLAB仿真的基础上,使用verilog实现,附带仿真波形图,实用性强
    2022-02-14 20:00:24下载
    积分:1
  • FIFO
    Simulation and Synthesis Techniques for Asynchronous FIFO Design
    2013-08-27 16:07:08下载
    积分:1
  • 696518资源总数
  • 105944会员总数
  • 20今日下载