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DisplayPort Link training optimization
说明： 介绍了Displayport规格中lind training的背景研究，设计和实现。(As the requirement for bandwidth continues to increase in the video market, retaining
the signal integrity becomes increasingly more difficult. For many of todays
commonly used video interfaces, there are devices that can be used to assist in this
matter. However, the use of such a device is only partially documented in the DisplayPort
specification for the receiving image device, which means that the receiving
side of the video link is free to choose its own implementation. This report presents,
together with background research and design decisions, a suggestion for such an
implementation. This implementation would need to be compatible towards a wide
range of possible video Source devices and DisplayPort cables.)
- 2021-01-11 16:48:49下载
- 积分：1
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Labview-Data-acquisition-card-
基于labview的数据采集系统，包括示波器和函数信号发生器，可以实现简单数据采集.(Labview-based data acquisition system, including oscilloscopes and function signal generator, can achieve a simple data acquisition.)
- 2014-01-15 21:26:04下载
- 积分：1
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mypro_synfifo
基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE(RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE)
- 2020-09-22 01:27:56下载
- 积分：1
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串口 自收自发程序
串口自收自发测试函数，开发环境quartus12.1，
波特率只设置了9600bps，可供测试开发板串口功能。
- 2023-05-06 08:00:03下载
- 积分：1
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lcd_1206
Verilog控制lcd1206显示源程序(Verilog control lcd1206 display source program)
- 2017-12-13 18:19:37下载
- 积分：1
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LightControl
说明： 经典的雷鸟车灯控制电路设计，各大高校实验必做题目(Thunderbird classic light control circuit design, major colleges and universities must do experimental subjects)
- 2011-03-05 09:49:32下载
- 积分：1
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chengfa_1
说明： FPGA实现四位数与四位数乘法，有仿真波形，合理利用FPGA资源(Four-digit and four-digit multiplication is realized by using FPGA. It has simulation waveform and makes rational use of the resources of the FPGA.)
- 2020-06-21 00:00:02下载
- 积分：1
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利用程序实现ADC_TLC549采样
本系统利用AD芯片TLC549进行AD采样并在数码管上显示TLC549AD采样程序 在数码管上显示 我们的TLC549AD是独立的模块，没有直接和FPGA链接。所以我们在使用时，要用杜邦线链接起来。视频教程适合我们21EDA电子的所有学习板
- 2022-08-16 16:10:23下载
- 积分：1
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05_fifo_test
说明： FIFO: First in, First out 代表先进的数据先出，后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO，根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)
- 2021-04-08 22:19:20下载
- 积分：1
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sim_uart
uart 收发器 verilog 代码，实现自收发功能
sys clk = 25m, baud 9600 停止位1， 无校验位；
代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过；
(verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )
- 2010-10-10 21:49:46下载
- 积分：1
