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HEX_DISPLAY
Simple vhdl description to show numbers on 7-segment s on Altera DE2 board.
- 2010-02-13 21:09:15下载
- 积分:1
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gtx_aurora_zc706_clock_module
对aurora模块时钟处理模块,实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)
- 2018-01-23 09:03:31下载
- 积分:1
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pipeline_booth_mult_16
用流水线的方法实现16位乘法器,运算速度快,消耗时钟资源少(Pipeline method to realize 16-bit multiplier, which is fast in operation and consumes less clock resources)
- 2020-09-29 18:17:44下载
- 积分:1
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mealy_sequence
实现米粒状态机
用verilog语言实现状态机的过程(Implement a state machine with a grain of rice verilog state machine language course)
- 2011-11-09 19:02:27下载
- 积分:1
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xapp774
基于tus5000评估板的VHDL源代码,用于超声波检测,xinlinx提供的(Based on the VHDL source code tus5000 uation board, used in ultrasonic testing, xinlinx provide)
- 2021-02-07 11:39:55下载
- 积分:1
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Verilog写的 8 位超前进位加法器
Verilog写的 8 位超前进位加法器-Verilog write 8-bit CLA
- 2023-01-24 03:30:03下载
- 积分:1
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基于FPGA的VHDL的电子琴
自己去年做的实训项目,基于FPGA的VHDL的电子琴,可实现自动演奏与手动演奏,手动演奏是用PS2键盘听过按键来实现电子琴的发音,并且用VGA显示音符与音键,本设计采用模块化设计,底层使用代码,通过例化成原理图,最终在底层实现原理图之间的连接。
- 2023-03-08 06:35:04下载
- 积分:1
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V2.tar
SDIO slave, written in verilog, does not support SPI mode.
- 2021-04-05 16:59:04下载
- 积分:1
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csbar(3) : X"E0000" to X"E01FF"
-- M68008 Address Decoder
-- Address decoder for the m68008
-- asbar must be 0 to enable any output
-- csbar(0) : X"00000" to X"01FFF"
-- csbar(1) : X"40000" to X"43FFF"
-- csbar(2) : X"08000" to X"0AFFF"
-- csbar(3) : X"E0000" to X"E01FF"
-- download from www.pld.com.cn & www.fpga.com.cn
--- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn
- 2022-02-26 21:53:57下载
- 积分:1
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18 x 18 华莱士树乘法器
经过测试的 VHDL 代码为 18 x 18 位华莱士树乘法器
- 2022-01-30 15:01:08下载
- 积分:1