登录
首页 » VHDL » Study the performance of state machine. Rar inspect the performance of state mac...

Study the performance of state machine. Rar inspect the performance of state mac...

于 2023-04-13 发布 文件大小:225.94 kB
0 82
下载积分: 2 下载次数: 1

代码说明:

状态机的性能考察.rar 状态机的性能考察.rar-Study the performance of state machine. Rar inspect the performance of state machine. Rar

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • TLC2543
    使用Verilog实现的AD采样,很有用的!(Implemented using Verilog AD sampling, very useful!)
    2020-11-18 15:59:39下载
    积分:1
  • 实用的程序代码,希望对大家有用,已经调试通过
    实用的程序代码,希望对大家有用,已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through
    2023-05-31 04:55:02下载
    积分:1
  • uart_zhiwen
    RS232的UART编程,包括波特率发生器模块,串口接受模块,串口发送模块(RS232 programming the UART, including the baud rate generator module, serial module to receive, send serial module)
    2009-04-10 10:57:05下载
    积分:1
  • fir.tar
    FIR滤波器的VHDL语言实现(The implement of FIR Filter based on VHDL)
    2004-10-19 10:14:56下载
    积分:1
  • 曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0,低→ 高的跳变表示为1。每个码元中间都要发生跳变,接收端可将此变化提取...
    曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0,低→ 高的跳变表示为1。每个码元中间都要发生跳变,接收端可将此变化提取出来作为同步信号,使接收端的时钟与发送设备的时钟保持一致-Manchester coding techniques that use voltage changes in 0 and 1. Provisions in the middle of each symbol hopping happen. High → low hopping express 0, low → high jump for the express one. Symbol between each transition must happen, this change in the receiver can be extracted as a synchronization signal to the receiving end of the clock and send the equipment to maintain the same clock
    2023-06-17 15:30:03下载
    积分:1
  • 实现PWM波型....使用VHDL语言
    实现PWM波型....使用VHDL语言-Realization of PWM waveform using the VHDL language ....
    2022-09-10 03:00:02下载
    积分:1
  • A3P600-PQG208
    Actel FPGA A3P600最小系统原理图,包含JTAG 、电源和封装 (Actel FPGA A3P600 minimum system schematics, including JTAG, power and packaging)
    2012-12-03 11:29:19下载
    积分:1
  • 32_lvds_test
    Xilinx 公司Spartan-6系列FPGA实现LVDS,带Modelsim仿真文件,已综合。(Xilinx Spartan-6 Series FPGA implements LVDS with Modelsim simulation file, which has been synthesized.)
    2020-11-30 20:59:27下载
    积分:1
  • 64point_FFT
    64点FFT代码 基4算法 Verilog(64-point FFT code radix-4 algorithm Verilog)
    2021-01-15 09:48:46下载
    积分:1
  • Experimental _EDA experimental guidance notes EDA books EDA technology and VHDL...
    _EDA实验讲义EDA实验指导书EDA技术与VHDL第3章EDA技术实用教程EAD技术与实践.等等资料-Experimental _EDA experimental guidance notes EDA books EDA technology and VHDL in Chapter 3 of EDA technologies utility EAD Technology and Practice Guide. And so on Information
    2022-09-22 04:20:06下载
    积分:1
  • 696518资源总数
  • 105547会员总数
  • 4今日下载