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wishbone
wishbone接口的设计，在交换机和MAC之间建立wishbone接口(the wishbone interface design, wishbone interface between the switch and MAC)
- 2012-12-05 12:22:24下载
- 积分：1
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alu
this file is vhdl code of alu
- 2016-05-29 16:35:58下载
- 积分：1
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help_lib
1.JESD204B协议
2.Xilinx的JESD204B phy 核手册
3.Xilinx的JESD204B rx_tx 核手册7.1
4.Xilinx的JESD204B rx_tx 核手册7.2
5.verilog实现串口发送(1.JESD204B protocol
2.Xilinx JESD204B PHY core manual
3.Xilinx JESD204B rx_tx core manual 7.1
4.Xilinx JESD204B rx_tx core manual 7.2
5.verilog to achieve serial transmission)
- 2017-11-15 16:09:22下载
- 积分：1
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本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.
本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.-I prepared for the sentinel division, the development of software for the ISE6.2 Xilinx, PAR through simulation.
- 2022-09-14 19:00:03下载
- 积分：1
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VHDLrefencebook
doulos公司出的VHDL学习工具，非常易学易懂！~(doulos company out of the VHDL learning tool, very easy to understand! ~)
- 2016-10-09 15:45:57下载
- 积分：1
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ahb_interface
AHB BUS, Master Slave Arbiter -- example(AHB BUS, Master Slave Arbiter)
- 2020-11-23 10:39:35下载
- 积分：1
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dds digital shift Signal Generator, full
dds数字移相信号发生器,功能齐全通过验证-dds digital shift Signal Generator, full-featured validated
- 2022-08-15 06:38:32下载
- 积分：1
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用verilog写的，基于查表法实现的LOG10运算器，在Altera FPGA中应用。...
用verilog写的，基于查表法实现的LOG10运算器，在Altera FPGA中应用。-It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.
- 2022-08-17 06:30:14下载
- 积分：1
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基于DDS的DA正弦波输出
Sample behavioral waveforms for design file sin_rom.vThe following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design sin_rom.v. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 3F0, 3F1, 3F2, 3F3, ...). The design sin_rom.v has one read port. The read port has 1024 words of 10 bits each. The output of the read port is unregistered. Fig. 1 : Wave showing read operation. The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until
- 2022-01-26 04:06:16下载
- 积分：1
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pin_lv1
一个简易的频率计，主要用检测在一定范围内的频率，当然频率过大会有误差(A simple frequency meter, mainly used for testing in a range of frequencies, of course, frequency of errors over the General Assembly)
- 2010-06-05 10:30:56下载
- 积分：1
