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用vhdl描写的通用异步改进dram控制器，经过编译器综合和仿真测试，符合设计要求。...
用vhdl描写的通用异步改进dram控制器，经过编译器综合和仿真测试，符合设计要求。-Using VHDL description Universal Asynchronous improved dram controller, through an integrated compiler and simulation testing, in line with the design requirements.
- 2022-04-19 09:59:57下载
- 积分：1
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Verilog代码。注册成功，对FPGA的使用标准单元库…
verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
- 2022-06-15 14:54:08下载
- 积分：1
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lowpass
低通滤波器（由matlab和simulink两种方法实现）源文件及图片示例(Low-pass filter) source file and photo examples (by the two methods matlab and simulink)
- 2013-03-13 18:36:40下载
- 积分：1
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This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...
This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
- 2022-04-07 07:47:24下载
- 积分：1
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DDS_signal_genarator
这是一个利用verilog语言编写的信号发生器的例子，值得参考(this is a code about signal generator by VIERILOG LANGUAGE!)
- 2013-12-23 10:12:52下载
- 积分：1
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基于Xilinx FPGA实现PS2键盘鼠标接口。版本1.0
基于Xilinx FPGA实现PS2键盘鼠标接口。版本1.0-Based on Xilinx FPGA realize PS2 keyboard and mouse interface. Version 1.0
- 2022-07-22 17:23:31下载
- 积分：1
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gpmc_fpga
实现arm与fpga之间通过gpmc总线通信(the device of fpga)
- 2015-10-27 16:44:25下载
- 积分：1
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不足20元的PCI设计，含ABEL源代码。
不足20元的PCI设计，含ABEL源代码。-PCI design less than 20Yuan ,including ABEL code
- 2022-01-24 17:08:50下载
- 积分：1
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4锁，移位，可以设置和更改您的密码。
四位密码锁，移位显示，可以设置和更改密码。-4 lock, shift, it can be set up and change your password.
- 2023-05-03 17:05:04下载
- 积分：1
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IIC EDID码配置
该代码完成了利用IIC总线接口，对HDMI芯片的EDID码进行配置的功能，已经验证在XILINX ML605开发板可用。
- 2022-02-01 20:27:01下载
- 积分：1
