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基于vhdl的PWM发生器
基于vhdl的PWM发生器-VHDL-based PWM generator
- 2022-03-04 15:27:12下载
- 积分：1
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ISPPCBforFPGA
Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB(Xilinx, Altera, ARM, AVR, S52, Lattice series FPGA download cable circuit diagram and PCB)
- 2009-12-14 16:55:35下载
- 积分：1
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本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设
计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数
（N+0...
本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设
计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数
（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可
通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使
用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.
- 2022-08-24 20:51:04下载
- 积分：1
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FPGA-IMPLEMENTATIONS-OF-THE-DES
FPGA based design and Implementation of Advanced Encryption Standard
- 2015-07-20 23:33:11下载
- 积分：1
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decodeLogDomainSimple
When the initial input falls between the Switch off point and Switch on point values, the initial output is the value when the relay is off.
- 2017-01-29 18:04:53下载
- 积分：1
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dingshi
定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)
- 2013-07-27 10:34:41下载
- 积分：1
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关于vhdl的一些例子
关于vhdl的一些例子-on some of the examples of VHDL
- 2022-01-28 04:13:20下载
- 积分：1
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ch8_1
8选1程序，是利用vhdl编写的，自己弄得还能用，上传下(8 Select a program is written using vhdl, allowed herself can use to upload the next)
- 2010-06-20 13:36:42下载
- 积分：1
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FPGA TRACKING SYS
下采样与灰度
- 2022-08-09 07:51:24下载
- 积分：1
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segment
This source is used to control 7 segments on FPGA boad
- 2014-11-10 13:33:13下载
- 积分：1
