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VHDL Storage/counter design
vhdl寄存/计数器设计-VHDL Storage/counter design
- 2022-01-26 02:37:06下载
- 积分：1
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这是我自己写的4人表决器源码，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！...
这是我自己写的4人表决器源码，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！-that I wrote four voting machine source code, In xilinx Spartan3E debugging has been successful, with the show to share with you!
- 2022-01-27 20:17:47下载
- 积分：1
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RapidIO_avalonst
RapidIO：使用Avalon-ST直通接口的实现方法，可以在fpga上实现(rapidio altera)
- 2017-05-31 22:50:11下载
- 积分：1
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USB1.1 IP核心控制设备，用硬件描述语言…
usb1.1的设备控制器IP核，是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.
- 2022-01-30 21:54:55下载
- 积分：1
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verilog例子很丰富，几个经典的,希望对初学者有所帮助
verilog例子很丰富，几个经典的,希望对初学者有所帮助-verilog examples of very rich, a few classic, and want to be helpful for beginners
- 2023-03-17 19:05:03下载
- 积分：1
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61EDA_C1202
Altera大学计划程序包，基于Nios II的源代码(Altera University program package, based on the Nios II source code)
- 2008-08-21 14:46:39下载
- 积分：1
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In the International Standards Organization Open Systems Interconnect (OSI) refe...
在国际标准组织开放式系统互联（OSI）参考模型下，以太网是第二层协议。10G以太网使用ＩＥＥＥ（电气与电子工程师学会）802.3以太网介质访问控制协议（ＭＡＣ）、ＩＥＥＥ 802.3以太网帧格式以及ＩＥＥＥ 802.3最小和最大帧尺寸。-In the International Standards Organization Open Systems Interconnect (OSI) reference model, Ethernet is the second-layer protocol. 10G Ethernet using the IEEE (Institute of Electrical and Electronics Engineers) 802.3 Ethernet Media Access Control Protocol (MAC), IEEE 802.3 Ethernet frame format, as well as the minimum and maximum IEEE 802.3 frame size.
- 2022-04-21 05:06:12下载
- 积分：1
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DE2_115_SD_Card_Audio_Player
该代码实现了对SD 卡的读写操作，是一个较好的范例。(The code achieves access reading SD CARD based on DE-2，It is
a good example。)
- 2012-08-14 00:29:47下载
- 积分：1
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DS18B20
DS18B20温度传感器的基于FPGA的编程通信，使用VHDL语言(DS18B20 temperature sensor based FPGA programming communication with VHDL)
- 2012-07-16 19:10:29下载
- 积分：1
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dianti
6层电梯设计，采用vhdl编写，能够实验电梯功能(6-story elevator design, using vhdl prepared, able to lift function experiments)
- 2014-04-06 11:41:34下载
- 积分：1
