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欢迎大家使用该程序，是在FPGA下使用开发的。请大家使用。
欢迎大家使用该程序，是在FPGA下使用开发的。请大家使用。-Welcome to use the program is to use FPGA development. Please use the.
- 2022-06-19 03:41:34下载
- 积分：1
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数字式移相信号发生器可以产生预置频率的正弦信号，也可产生预置相位差的两路同频正弦信号，并能显示预置频率或相位差值；...
数字式移相信号发生器可以产生预置频率的正弦信号，也可产生预置相位差的两路同频正弦信号，并能显示预置频率或相位差值；-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that the preset frequency or phase difference value;
- 2023-07-21 04:20:04下载
- 积分：1
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design a module from a trip data flow channeling Lane detected bitstream "1...
设计一个模块，从一个窜行数据流里检测出码流“11100”，这个模块包括reset,clk,datain及输出端pmatch-design a module from a trip data flow channeling Lane detected bitstream "11100", this module includes reset, clk, datain and output pmatch
- 2022-07-06 13:42:26下载
- 积分：1
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In communication systems channel poses an important role. channels can convolve...
In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear.
and more sevear is such distortion is random.
To handle this, multipath affected channels require Equalizers at receaver end.
such equalizer uses different learning Algorithms for identifying channels continuously.
This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton
It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.
- 2022-02-24 17:03:03下载
- 积分：1
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flv的vhdl教学文件:在线调试
自己慢慢欣赏吧
flv的vhdl教学文件:在线调试
自己慢慢欣赏吧-flv file of VHDL Teaching: Online debug their慢慢欣赏吧
- 2022-05-22 02:55:52下载
- 积分：1
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Noc
说明： credit base network on chip(network on chip (noc))
- 2020-06-19 11:40:02下载
- 积分：1
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这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章，实用性很强的，在这里也感谢这篇文章的作着...
这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章，实用性很强的，在这里也感谢这篇文章的作着-This is a description language with verilog viterbi decoding and rake receiver of the article, very practical, here are grateful for this article was
- 2022-05-13 15:53:30下载
- 积分：1
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xilinx_usb_drivers_win10_x64
win10的xilinx usb驱动，较新版本(Xilinx USB driver for win10, newer version)
- 2021-03-11 17:09:26下载
- 积分：1
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myuart
使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路(Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas)
- 2013-07-25 11:45:57下载
- 积分：1
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全部通过，是我的精心设计，完全满足初学者的要求。
全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.
- 2022-02-20 15:52:11下载
- 积分：1
