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Flash
FPGA Verilog控制FLASH片外读写(Verilog Controls FLASH Out-of-Chip Read-Write)
- 2020-06-22 21:40:01下载
- 积分：1
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cic_dec_8_five
CIC抽取滤波器，抽取系数8,verilog版本，用于数字下变频(CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion)
- 2010-03-02 12:53:31下载
- 积分：1
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SPI_tx_ATtiny2313
ya 3an zok omkom 9a7ba
- 2014-08-12 02:41:54下载
- 积分：1
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This is an FPGA
这个是一个基于FPGA的SDRAM控制器系统，实现对SDRAM的读写操作，用来实现时序的控制-This is an FPGA-based SDRAM controller system, the read and write operations to SDRAM to achieve the control of timing
- 2022-02-02 20:49:24下载
- 积分：1
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sin and cos with cordic VHDL
该模块采用cordic算法计算正弦和余弦，并采用参数化方式实现。 ；包中存在其他模块。
- 2022-05-25 06:14:20下载
- 积分：1
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ad9226
FPGA驱动adc9226，高精度高速度。(ad9226 by FPGA)
- 2015-08-04 10:03:20下载
- 积分：1
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phase_test
VHDL,简易音频数字相位表的设计与实现 数字相位测量仪在工业领域中经常用到的一般测量工具，主要应用与同频率正弦信号间的相位差的测量显示。
本系统采用FPGA实现测量的核心部分，主要由数字鉴相、累加计数器、控制器以及寄存与显示译码电路组成。该系统硬件电路简单，整个系统采用硬件描述语言VHDL作为系统内部硬件结构的描述手段，在XILINX公司的ISE9.1的软件支持下完成。可以对20Hz~20kHz频率范围内的音频信号进行采样鉴相处理，并将数据传回FPGA进行相位差计数累加、测量运算，最后送显示译码电路显示，测相范围为 ，相位测量误差 < 。
经测试结果验证，本系统充分利用FPGA对数据的高速处理能力，是系统设计高效、可靠，处理速度快，稳定性高，易于实现。
(VHDL, simple audio digital phase Table Design and Implementation of the digital phase meter general measurement tools are often used in the industrial field, the measurement of the phase difference between the main application with the same frequency sinusoidal signal. The system uses the FPGA implementation of the core part of the measurement, mainly by the digital phase, cumulative counter, the decoding circuit of the controller as well as storage and display. The system hardware circuit is simple, and the entire system using hardware description language VHDL system means a description of the internal hardware structure, completed in the XILINX company ISE9.1 software support. The audio signal in the frequency range of 20Hz ~ 20kHz sampling KAM-phase process, and the data returned FPGA retardation counted accumulation measuring operation, and finally sent to the decoding circuit, the scope of the measurement phase, the phase measurement error < . The test results verify the full u)
- 2012-09-24 10:11:57下载
- 积分：1
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DDS Verilog 代码。包含英文文档说明
DDS Verilog 代码。包含英文文档说明-DDS Verilog code. Containing the English documentation
- 2022-10-25 06:35:03下载
- 积分：1
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Verilog语法
说明： Verilog语法教程，适合初学者，详细(Verilog instruction book)
- 2019-05-04 16:07:18下载
- 积分：1
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用VHDL写的计算器，实现加减功能以及ＶＧＡ显示功能，适合VHDL初学者使用。...
用VHDL写的计算器，实现加减功能以及ＶＧＡ显示功能，适合VHDL初学者使用。-VHDL write calculators, Modified functions and achieve VGA display, VHDL for beginners.
- 2022-06-12 21:10:47下载
- 积分：1
