-
UMC_90nm_1P9M_LOGIC_MIXED_MODE_Process_TLR_V1.1
UMC 90nm design kit. please read before using thee models.
- 2013-02-02 11:24:38下载
- 积分：1
-
EP2C35开发板官方原理图,是altera的官方资料。是fpga电路设计的很好参考典范。...
EP2C35开发板官方原理图,是altera的官方资料。是fpga电路设计的很好参考典范。-EP2C35 official development board schematics, is altera of official information. Fpga circuit design is a good reference model.
- 2022-07-01 18:31:57下载
- 积分：1
-
12864hanzixianshi
基于FPGA 的12864液晶显示汉字，用verilog编写的。(12864 liquid crystal display Chinese characters based on FPGA, written in verilog.)
- 2021-04-27 15:48:44下载
- 积分：1
-
freeDev数字应用开发板中的七段数码管的IP核的verilog实现
freeDev数字应用开发板中的七段数码管的IP核的verilog实现-freeDev digital application development boards in the seven-segment digital tube of the IP core implementation of the verilog
- 2022-01-31 19:57:07下载
- 积分：1
-
这是一本关于VHDL编程的书籍,网上突然发现的,相信对相关人员会有所用途....
这是一本关于VHDL编程的书籍,网上突然发现的,相信对相关人员会有所用途.-This is a book on VHDL programming, on-line suddenly found, I believe that the relevant staff will be use.
- 2023-02-06 08:50:07下载
- 积分：1
-
FFT 32 BIT VHDL PROGRAM
FFT 32位VHDL编程
- 2022-02-25 15:36:41下载
- 积分：1
-
Coding Styles for if Statements and case Statements
Coding Styles for if Statements and case Statements
- 2022-02-09 23:54:06下载
- 积分：1
-
采用systemc语言设计了一个状态机，主要包括两个进程，仿真结果表明状态机可以正常工作...
采用systemc语言设计了一个状态机，主要包括两个进程，仿真结果表明状态机可以正常工作-Systemc language designed using a state machine, mainly consists of two processes, the simulation results show that the state machine can work properly
- 2022-03-17 09:47:30下载
- 积分：1
-
索FPGA Verilog使用ROM和RAM实现高dcfifo
alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM
实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
- 2023-05-06 14:25:03下载
- 积分：1
-
edge_detect_p
用于检测信号上升沿，输出与时钟相关的正脉冲(Detect the rising edge of the signal)
- 2012-03-27 14:49:21下载
- 积分：1
