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vga接口的工程实现，基于altera环境，需要的可以
vga接口的工程实现，基于altera环境，需要的可以-vga interface engineering implementation, based on altera environment, need to take a look at
- 2023-04-22 21:05:04下载
- 积分：1
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这是一个语音程序,通过VHDL编译了.大家可以直接调用.其中还包括了键盘程序有需要可以下来...
这是一个语音程序,通过VHDL编译了.大家可以直接调用.其中还包括了键盘程序有需要可以下来-This a voice procedures, through a VHDL compiler. you can directly call. It also includes a keyboard procedures need to look at it down
- 2022-06-13 01:51:36下载
- 积分：1
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xilinx simulator programme of serial port
xilinx的串口仿真程序-xilinx simulator programme of serial port
- 2022-11-08 03:05:05下载
- 积分：1
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8位CPU软核设计与应用研究
8位CPU软核设计与应用研究-8-bit CPU design and application of soft-core research .......
- 2022-03-21 23:18:32下载
- 积分：1
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daima
Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。
(Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)
- 2014-12-11 20:16:04下载
- 积分：1
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SineGen
Basic VHDL code to create a sine wave generator for an FPGA board.
- 2014-01-24 01:04:15下载
- 积分：1
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2ASK
2ask调制与解调的源代码，经过测试可用(2ask modulation and demodulation source code is available, tested)
- 2012-12-09 21:27:49下载
- 积分：1
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sobel
Verilog代码实现Sobel算子，包括整个工程，仿真也有。。仿真表明该程序能实现Sobel 算子硬件实现(Verilog，Sobel Operator)
- 2011-05-10 21:11:21下载
- 积分：1
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dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
- 2022-11-12 18:25:03下载
- 积分：1
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在SOPC Builder的UART IP核接口
UART RS232 IPCORE for sopc builder
-RS232 UART IPCORE for sopc builder
- 2022-03-04 13:15:40下载
- 积分：1
