登录
首页 » VHDL » 利用两个半加器来组成的全加器,是简单的vhdl语言入门

利用两个半加器来组成的全加器,是简单的vhdl语言入门

于 2023-08-01 发布 文件大小:815.00 B
0 136
下载积分: 2 下载次数: 1

代码说明:

利用两个半加器来组成的全加器,是简单的vhdl语言入门-The use of two and a half adder to form the full adder is a simple entry-vhdl language

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • ping
    乒乓球游戏,用led灯控制水上乒乓球,选择了控制键进行操作。详细信息请参见自述
    2023-02-19 03:35:03下载
    积分:1
  • urisc
    自己用verilog编写的urisc程序,调试成功,压缩包里有仿真图像,值得学习参考。(Written in verilog urisc program debugging, simulation image compression bag, worth learning reference.)
    2021-04-22 17:38:48下载
    积分:1
  • FPGAPDSCDMA
    上海交大关于基于FPGA的DSCDMA的实现的毕业设计(Shanghai Jiaotong University based the FPGA DSCDMA, achieve graduation design)
    2013-02-10 14:31:46下载
    积分:1
  • gwnseq
    verilog产生高斯白噪声,gwn_en信号产生使能,gdata是幅度服从高斯分布,功率谱密度为定值的高斯白噪声序列,共10位(现实中只能够做到带限,跟dac输出带宽有关,我的系统只能做到300kHz)(verilog Gaussian white noise, gwn_en signal enabled, gdata amplitude Gaussian distribution, power spectral density of white Gaussian noise sequence value, a total of 10 (in reality can only be band-limited, with dac output bandwidth related, My system can do 300kHz))
    2014-06-13 13:18:45下载
    积分:1
  • PCI_arbi
    PCI arbi verilog source code
    2009-03-29 18:04:41下载
    积分:1
  • -Elliptic
    We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coprocessor can be adapted both prime field and binary field, also contains a control unit with 256 bit serial and parallel operations , which provide integrated highthroughput with low power consumptions. Our scalar multiplier architecture operation is perform base on clock rate and produce better performance in term of time and area compared to similar works. We used Verilog for programming and synthesized using Xilinx Vertex II Pro devices. Simulation was done with Modelsim XE 6.1e, VLSI simulation software from Mentor Graphics Corporation especially for Xilinx devices.
    2012-02-09 10:48:50下载
    积分:1
  • RTL8369-design-kit-v3_5
    RTL8369开发资料,包括手册,图纸,Layout说明等等(RTL8369 development information, including manuals, drawings, Layout Guide.)
    2014-12-07 13:04:30下载
    积分:1
  • 很多实用的例程,包括触发器,译码器,多路选择器
    很多实用的例程,包括触发器,译码器,多路选择器-A lot of useful routines, including the flip-flop, decoder, MUX
    2022-03-06 03:11:07下载
    积分:1
  • 四位静态数码管控制器,含详细的中文注释,VERILOT源码....
    四位静态数码管控制器,含详细的中文注释,VERILOT源码.-4 static digital tube controller, with detailed notes in Chinese, VERILOT source.
    2022-03-29 22:12:43下载
    积分:1
  • verilog-axi-master
    说明:  Verilog AXI Components Readme GitHub repository: alexforencich verilog-axi
    2020-11-04 14:39:51下载
    积分:1
  • 696516资源总数
  • 106571会员总数
  • 2今日下载