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verilog实现的“并行输入、并行输出移位寄存器”
verilog实现的“并行输入、并行输出移位寄存器”-verilog to achieve a " parallel input, parallel output shift register"
- 2023-06-06 17:30:03下载
- 积分:1
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vhdl
vhdl表示与综合,原书第二版,中文版,比较全,用超星打开-vhdl
- 2023-05-18 10:30:04下载
- 积分:1
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RSA密码芯片的FPGA实现[1].part1.rar
RSA密码芯片的FPGA实现[1].part1.rar...
RSA密码芯片的FPGA实现[1].part1.rar
RSA密码芯片的FPGA实现[1].part1.rar-RSA password chip FPGA realization of [1]. Part1.rarRSA password chip FPGA realization of [1]. Part1.rar
- 2022-08-13 06:54:28下载
- 积分:1
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2003101190493221
还好用,大家一起来看下,不错的图书管理软件啊 ,呵呵(Fortunately with, everyone look, the good library management software, ah, huh, huh)
- 2010-09-14 13:08:40下载
- 积分:1
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SD卡上有音频部分!希望对大家有用!
有关于SD卡的音频部分!希望对大家有用!-SD cards have on the audio portion! Hope useful for everyone!
- 2022-02-05 13:29:26下载
- 积分:1
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lunwen
一个完整的基于FPGA的IIR低通滤波器的设计方案,是一个研究生论文(master and doctor dissertation)
- 2013-05-12 20:01:14下载
- 积分:1
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电梯
利用verilog编写的电梯程序,实现基本的电梯运行功能(Elevator program written by Verilog)
- 2018-11-25 11:39:50下载
- 积分:1
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一个以太网卡的硬件描述,可以参考进行设计网卡芯片。
一个以太网卡的硬件描述,可以参考进行设计网卡芯片。-an Ethernet card hardware description, reference card chip design.
- 2023-08-18 05:00:03下载
- 积分:1
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gtwizard_254_127_ex_1113_3
配置GTH ip的例子工程,选用7 series 芯片的GTH 113quad的四个通道,在程序中每个链路利用自己的恢复时钟进行数据解码,所以四个通道可以各自独立运行;成功工作在2.54Gb/s的链路状态,长时间(>24小时)的测试,误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)
- 2019-06-17 21:33:56下载
- 积分:1
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基于Xilinx fpga的ddr2 控制器设计方法
基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2
- 2022-08-11 18:36:22下载
- 积分:1