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VHDL语言设计；功能描述：键盘扫描，不包含去抖电路
VHDL语言设计；功能描述：键盘扫描，不包含去抖电路-VHDL language design Function description: the keyboard scanning, does not contain a circuit debounced
- 2022-08-26 08:21:49下载
- 积分：1
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FPGA_SSI
说明： 文档中的verilog代码实现了FPGA与SSI总线的数据协议链接(Verilog code in the document of the FPGA data bus protocol and SSI links)
- 2021-04-19 17:08:51下载
- 积分：1
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任意基数分频VERILOG代码，经过了编译，可以修改数字改变分频。...
任意基数分频VERILOG代码，经过了编译，可以修改数字改变分频。-Arbitrary base frequency Verilog code, after compilation, the figures can be amended to change the frequency.
- 2022-08-10 12:37:41下载
- 积分：1
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一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码
一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码-VerilogHDL language based on the 16-bit multiplier of the booth algorithm and test code
- 2022-02-07 12:03:36下载
- 积分：1
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uart
通过串口发送，实现FPGA与stm32的dds发生器(Implementation of DDS generator)
- 2018-11-28 09:19:29下载
- 积分：1
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FPGA
基于ＦＰＧＡ实现移位乘法功能，已经验证，十分好用。-FPGA-based multiplication realize shift function, has been verified, is very easy to use.
- 2022-02-07 13:03:46下载
- 积分：1
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硬件描述语言Verilog
硬件描述语言Verilog-Verilog hardware description language
- 2022-07-26 19:00:22下载
- 积分：1
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Nios-II
数字电路的设计。以软件方式实现硬件电路，功能强大，开发容易。(Digital circuit design. With software to realize the hardware circuit, powerful, development easy.
)
- 2011-12-03 09:47:56下载
- 积分：1
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JOP of RAM VHDL source code, classic classics, difficult to find a good price.
JOP的RAM VHDL源码，经典的经典，不易找到的好东东，-JOP of RAM VHDL source code, classic classics, difficult to find a good price.
- 2022-10-01 16:00:03下载
- 积分：1
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s
说明： 反应力测试 利用图片的变换根据用户点击的反应时间判断(Reaction force measurement using the picture of the transformation reaction time based on user clicks judgment)
- 2013-06-02 20:59:41下载
- 积分：1
