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b4b52
4b5b编码器实现，初学者资源，简单的逻辑电路实现(4b5b encoder implementation, resources for beginners)
- 2020-12-03 08:59:25下载
- 积分：1
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Quartus flv configuration and commissioning of the
QUARTUS 的配置及调试
flv的
-Quartus flv configuration and commissioning of the
- 2023-08-05 13:40:04下载
- 积分：1
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interpolation_shaping_filter
内插成型滤波器的FPGA实现，可根据需要配置不同的内插倍数，Quarter II环境编译，可直接使用(Interpolation shaping filter FPGA, can be equipped with different interpolation factor, Quarter II compiler environment, can be used directly)
- 2013-11-12 21:13:46下载
- 积分：1
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lvds_ctr_top
说明： 用verilog编写的LVDS接口驱动程序，采用IOSERDES技术实现，经过Spartan6 FPGA调试验证，有完整的工程。(The LVDS interface driver written in verilog is implemented using IOSERDES technology. After Spartan6 FPGA debugging and verification, there is a complete project.)
- 2020-03-16 10:29:10下载
- 积分：1
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完成十余卷积过程，简单方便，能够这样那样这样，sorry
完成十余卷积过程，简单方便，能够这样那样这样，sorry-Convolution process more than a decade to complete, simple and convenient, this can be done this way, sorry
- 2022-10-31 06:20:03下载
- 积分：1
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Dec_mul
时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。
OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system.
OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
- 2013-12-26 18:00:24下载
- 积分：1
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CC
说明： 802.16d 的卷积编码和解码的VHDL实现(802.16d cc encoding and decoding,writing in VHDL)
- 2015-05-14 23:05:54下载
- 积分：1
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VHDLDesignandFPGAImplementationofLDPCDecode
说明： 一篇关于LDPC解码算法的FPGA用VHDL实现的PDF文件，老外写的，还可以，可以参考，欢迎大家下载！(A PDF about the FPGA implementation of LDPC algorithm, written by foreigners, but also, you can refer to, welcome to download!)
- 2020-03-23 20:33:51下载
- 积分：1
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LEDtest
vhdl 实现fpga 闪灯控制 流水线闪灯 还用signalTAP进行检测，给初学者参考(vhdl fpga flash control lines to achieve flash is also used signalTAP testing, to advanced users)
- 2010-06-10 16:27:57下载
- 积分：1
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AD9914原理图和gerber以及BOM表
DDS VHDL include everything of dds
AD9914
- 2019-06-03 09:40:52下载
- 积分：1
