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pll
用FPGA实现数字锁相环，开发环境为ISE(Using FPGA digital phase-locked loop, development environment for ISE)
- 2021-03-19 18:29:19下载
- 积分：1
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mips3
Modelsim+DC开发的4级流水线结构的MIPS CPU(mips 4level cpu)
- 2020-08-08 11:18:30下载
- 积分：1
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count16
制作16位流水灯，实现LED模块对于拨杆0和1的识别(Making 16-bit pipeline lamp to realize the recognition of dial rod 0 and 1 by LED module)
- 2020-06-24 01:20:02下载
- 积分：1
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maichongceliang
对于已获得的脉冲包络采样序列，需测量的脉冲特征参数主要有：脉冲幅值(PA)、脉冲到达时间(TOA)和脉冲宽度(PW)。实际测量中，脉冲波形的形状是各种各样的，但其主要的参数有脉冲幅度、脉冲宽度、脉冲周期、脉冲占空比、脉冲前沿(上升时间)、脉冲后沿(下降时间)、脉冲上冲、脉冲下冲、脉冲下垂、脉冲顶部不平度等，脉冲参数的计量主要就是对这些参数进行计量。本程序包实现基于FPGA实现脉冲宽度和重复周期的测量。(Who have access to the pulse envelope sample sequence, the pulse measurement to be the main characteristic parameters are: pulse amplitude (PA), pulse time of arrival (TOA) and pulse width (PW). The actual measurement, the pulse shape is a wide variety of shapes, but its main parameters of the pulse amplitude, pulse width, pulse period, pulse duty cycle, pulse leading edge (rise time), pulse along (down time), the red pulse, pulse undershoot, pulse droop, pulse irregularities, such as at the top, the measurement of pulse parameters is mainly the measurement of these parameters. The package FPGA-based pulse width and repetition to achieve the measurement cycle.)
- 2009-07-08 14:32:08下载
- 积分：1
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divid5_VERILOG
VERILOG实现无分频时钟，包括测试文件，经过验证可用(VERILOG is no difference between the frequency of the clock implementation, including test papers, can be used after authentication)
- 2009-03-30 15:11:30下载
- 积分：1
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一款240＊128的LCD模块在ALTERA FPGA NIOS中的应用，自己写的AVALON总线IP，包括所有源码，可轻松用于NIOS中，供大家参考...
一款240＊128的LCD模块在ALTERA FPGA NIOS中的应用，自己写的AVALON总线IP，包括所有源码，可轻松用于NIOS中，供大家参考-A 240* 128 LCD module in the ALTERA FPGA NIOS application, write your own AVALON Bus IP, including all source code can be easily used in NIOS for reference
- 2022-07-03 08:05:54下载
- 积分：1
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138
用vhdl 语言实现138译码器，用vhdl 语言实现138译码器，(vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl )
- 2009-04-21 12:32:17下载
- 积分：1
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VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验...
VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验-VHDL by VGA interface standards, digital image signal conversion into a standard VGA format. Suitable for the pilot study
- 2022-05-08 02:59:08下载
- 积分：1
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Verilog代码。注册成功，对FPGA的使用标准单元库…
verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
- 2022-04-14 16:29:39下载
- 积分：1
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收集的QuartusII的使用手册，包含了几个pdf文件，比较不错的参考手册...
收集的QuartusII的使用手册，包含了几个pdf文件，比较不错的参考手册-Collected QuartusII s manual contains a number of pdf files, compare a good reference manual
- 2023-05-22 15:35:09下载
- 积分：1
