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spi_2
说明： DAC3283 寄存器初始化，SPI驱动(Dac3283 register initialization, SPI drive)
- 2020-03-14 09:56:50下载
- 积分：1
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高级加密标准AES的FPGA实现，支持128，256密钥长度格式
高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
- 2022-03-25 02:47:08下载
- 积分：1
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Construction-and-Experimental-Evaluations-of-User
Construction and Experimental Evaluations of User-Centered Power
- 2011-11-29 08:35:34下载
- 积分：1
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实现spi接口的传输，并多外接EEPROM读写数据
实现spi接口的传输，并多外接EEPROM读写数据-Spi interface to achieve the transfer, and multiple external EEPROM read and write data
- 2022-02-06 14:13:33下载
- 积分：1
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include UART port of VERILOG source, the program tested in FPGA, as chip design,...
包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
- 2022-06-01 13:44:15下载
- 积分：1
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cpu8bit
这是一个计算机组成原理综合性实验：设计8位cpu。该cpu是8bit的代码，包含有4个寄存器，一个存储器，还有alu以及控制器。一共可以实现16条指令。(This is a computer composition principle of comprehensive experiment: Design 8 cpu. The cpu is 8bit code contains four registers, a memory, as well as alu and controllers. A total of 16 instructions can be achieved.)
- 2020-07-01 08:40:01下载
- 积分：1
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altera 公司的15IP源码
亲自测试还不错 有DIV, CONTER
altera 公司的15IP源码
亲自测试还不错 有DIV, CONTER-ALTERA the 15IP source personally tests are also good DIV, CONTER
- 2022-03-13 02:56:46下载
- 积分：1
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alarm
闹钟设计，VHDL，源代码。闹钟设计，VHDL，源代码。(Alarm clock design, VHDL, the source code.)
- 2011-05-23 18:30:29下载
- 积分：1
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simple_cpu
初学cpu结构的很好的verilog代码的示例，适合初学者(novice cpu structure of the good verilog code examples for beginners)
- 2007-03-03 01:05:16下载
- 积分：1
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build synthesizer on a de2 dev fpga board
build synthesizer on a de2 dev fpga board
- 2023-07-24 00:25:04下载
- 积分：1
