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AHB_to_Wishbone_Verilog
说明: 该源代码包是AHB总线到Wishbone总线的交接器,包括以下4个部分:RTL源代码,测试平台,软件测试程序,说明文档。(This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.)
- 2021-01-22 14:48:40下载
- 积分:1
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ulpiereport.tar
开源的ULPI IP核,可用于USB3300芯片的开发(openSource ULPI IP core which could be used for USB3300 chip development)
- 2020-07-02 06:40:02下载
- 积分:1
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RAM存储器: 设定16 个8 位存储单元。如果read= 1 则dataout<=mem(conv_integer(address)). 如果write
RAM存储器: 设定16 个8 位存储单元。如果read= 1 则dataout
- 2022-08-05 20:01:41下载
- 积分:1
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verilog user guide
verilog语法说明,包含verilog golden reference guide,verilog 2001语法(verilog golden reference guide)
- 2018-05-08 22:50:16下载
- 积分:1
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Quartus
QuartusII多路选择器,数字电路环境,大三EDA技术实验(Quartus,chosen conductos in matheathics field)
- 2012-10-30 16:26:11下载
- 积分:1
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MP3译码器的VHDL代码
MP3解码器的VHDL源代码 ,很实用的,设计时可以参考 ,很罕见的完整MP3 decoder源码 -VHDL code for MP3 decoder
- 2022-05-07 23:05:49下载
- 积分:1
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algorithm_design_and_logic_implemention
本书作者为夏宇文,详细讲解了从算法设计与验证到硬件逻辑实现的过程,要求读者有一定的verilog基础(This book author XIA Yu-Wen gave a detailed account from algorithms to hardware logic design and verification of implementation process, requiring readers to have some basis for verilog)
- 2009-11-11 21:19:03下载
- 积分:1
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UART_real_time_clock
This is an UART real time clock
- 2009-06-07 01:21:41下载
- 积分:1
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VHDL编写的flash控制器源代码.包含testbench。
VHDL编写的flash控制器源代码.包含testbench。-Prepared by flash controller VHDL source code. Contains testbench.
- 2022-03-18 10:11:40下载
- 积分:1
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cn1
在MATLAB的SIMULINK中,用DSPBUILDER实现计数功能,控制LED指示灯.(In MATLAB SIMULINK, DSPBUILDER is used to realize counting function and control LED indicator lamp.)
- 2018-08-16 15:35:47下载
- 积分:1