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verilog motor control
verilog motor control
- 2022-09-01 04:55:02下载
- 积分：1
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VHDL
说明： 运用VHDL描述函数发生器的各个波形，可有构成多功能函数发生器。(VHDL description of the use of various function generator waveforms, can constitute a multi-purpose function generator.)
- 2009-08-18 16:54:24下载
- 积分：1
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a
说明： 用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写(verilog ise divider)
- 2013-07-21 15:03:31下载
- 积分：1
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TCON
用verilog编程的TCON模块（时序控制器）的程序(Verilog programming module with TCON (timing controller) program)
- 2013-06-26 10:50:59下载
- 积分：1
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vhdl code for counterand detemines how counter
works
vhdl code for counterand detemines how counter
works
- 2023-03-20 20:40:03下载
- 积分：1
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fpga_dsp_simple
dsp和fpag通信的测试程序，包含整个工程和signaltap测试信号。(the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.)
- 2013-04-14 15:17:20下载
- 积分：1
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ldpc
最近在做毕设，ldpc码的编解码实现，这个是verilog实现。(Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.)
- 2021-05-14 15:30:02下载
- 积分：1
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zuoye2
主要编写了一组二进制数据通过根升余弦滤波器后的波形，但并没有使用ISE内部的FIR滤波器内核，该程序相当于编写了一个根升余弦滤波器。(Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.)
- 2013-09-18 15:24:13下载
- 积分：1
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CODE_VHDL_COUNTING 0 到 9，使用按钮 (Đếm 慈 0 đến 9 hiển 施耐 1 带领 7 đoạn sử dụng nút nhấn để điều khiển)
CODE_VHDL_COUNTING 0 到 9，使用按钮 (Đếm 慈 0 đến 9 hiển 施耐 1 带领 7 đoạn sử dụng nút nhấn để điều khiển)
Với bài này tôi sử dụng một nút nhất để một nút nhấn đế bắt đầu đếm dữ liệu 将重置。
- 2022-07-25 16:14:59下载
- 积分：1
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6713emiftofpgatopci,这个是完整的一套从6713的emif到fpga的双口ram，然后主机通过9054到双口ram，交换数据完成
6713emiftofpgatopci,这个是完整的一套从6713的emif到fpga的双口ram，然后主机通过9054到双口ram，交换数据完成-6713emiftofpgatopci, this is a complete set of the EMIF from 6713 to the FPGA
- 2022-01-25 23:08:47下载
- 积分：1
