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DDS_BPSK
基于DDS的BPSK调制器设计Verilog源码( U57FA u4E8.08 u868)
- 2017-04-28 11:44:46下载
- 积分：1
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SCRAMBLER
32位扰码器的verilog代码，编译通过(The Verilog code of 32_bit scrambler)
- 2009-11-24 14:51:38下载
- 积分：1
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黄金时段介绍STA
PrimeTime Intro to STA
-PrimeTime Intro to STA
- 2022-12-10 13:05:05下载
- 积分：1
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RANGEN
2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)
- 2020-10-27 17:09:59下载
- 积分：1
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ff_const_mul
说明： 常系数有限域乘法器，verilog DHL源码(Constant coefficient finite field multiplier, verilog DHL source)
- 2011-02-19 21:09:36下载
- 积分：1
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ALTERA_FPGA_SDRAM
使用ALTERA的FPGA控制SDRAM的verilog程序(Use ALTERA s FPGA to control SDRAM s verilog program)
- 2017-03-30 00:31:53下载
- 积分：1
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soble
基于FPGA的Sobel边缘检测算法的实现与仿真。此程序提供算法的verliog实现。(Implementation and Simulation of Sobel edge detection algorithm based on FPGA. This program provides the verliog implementation of the algorithm.)
- 2017-08-30 16:06:04下载
- 积分：1
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wbm
用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.(algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company's paid Multiplier ip core.)
- 2006-07-12 14:49:35下载
- 积分：1
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detection of the following sequence ‘10110110’in VHDL
detection of the following sequence ‘10110110’in VHDL
- 2023-04-17 19:05:03下载
- 积分：1
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frequency
数字频率计，测量范围0-1GHZ,测周测频自动转换，精度极高，花了很长时间，不过还是有一点点小问题，有待改进.(Digital frequency meter, range 0-1GHZ, automatic conversion measured weekly frequency measurement, high precision, took a long time, but still a little small problems to be improved.)
- 2011-08-11 00:51:18下载
- 积分：1
