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half_adrrrrder
FPGA上的一个半加器实例程序，通过测试，可以直接运行在fpga开发板上。(One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board)
- 2013-12-01 12:01:31下载
- 积分：1
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fpga0023202323
FPGA时序分析说明。对于高速时钟设计中的时序分析与约束有帮助(FPGA,TIME)
- 2010-11-01 15:49:34下载
- 积分：1
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一篇用VHDL实现快速傅立叶变换的论文
一篇用VHDL实现快速傅立叶变换的论文，包括原理分析和代码实现，印度圣雄甘地大学M.A.学院提供(VHDL with a Fast Fourier Transform papers, including the principle of analysis and implementation of the code, the Mahatma Gandhi Institute of the University of Marat)
- 2004-10-05 11:06:01下载
- 积分：1
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these files are written in verilog but i am uploading in text format
these files are written in verilog but i am uploading in text format
- 2022-01-26 00:53:26下载
- 积分：1
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VHDL
用VHDL语言实现一Mealy型时序电路，并做时序仿真和功能仿真检验正确与否。(Implement a Mealy-type sequential circuits using VHDL language, and do functional simulation and timing simulation test correct.)
- 2014-03-20 14:44:28下载
- 积分：1
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USB
实现FPGA与PC通信的USB2.0接口,采用verilog语言实现(Implementation of FPGA and PC communication USB2.0 interface, using Verilog language to achieve)
- 2021-02-22 21:59:41下载
- 积分：1
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wola
WOLA polyphase filter加权跌接累加FFT信道化技术(WOLA polyphase filter bank)
- 2020-09-28 14:57:45下载
- 积分：1
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car
基于Xilinx公司的ISE软件开发的智能循迹避障小车的源代码，用Verilog语言，传感器有红外传感器以及超声波传感器(Xilinx' s ISE-based software development intelligent car tracking avoidance source code, using Verilog language, the sensor has an infrared sensor and ultrasonic sensors)
- 2015-03-21 18:06:18下载
- 积分：1
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ccd
自己写的一个tcd1209d的时序驱动代码，是用verilog语言编写的，可以借鉴(Of write a tcd1209d of timing-driven code, Verilog language, can learn from)
- 2021-04-08 09:39:00下载
- 积分：1
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本程序实现不同频率时钟的产生及其相互转化
本程序实现不同频率时钟的产生及其相互转化-this program different clock frequencies to the formation and transformation
- 2022-03-06 09:31:43下载
- 积分：1
