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sqrt_pipeline
Matlab - to hdl code for square root
- 2020-06-17 12:20:02下载
- 积分：1
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PWM
通过一个计数器来实现输出信号的占空比要求，可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)
- 2020-06-16 13:20:02下载
- 积分：1
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dvb_s2_ldpc_decoder_latest.tar
LDPC COded OFDM System
- 2013-02-09 21:41:33下载
- 积分：1
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exp_rom
通过MATLAB产生单脉冲信号的数据，存储下来作为verilog代码实现的DDS的数据源，用于验证DA数据的ddio的调试是否有问题。(The data of monopulse signal generated by MATLAB is stored as the data source of DDS implemented by Verilog code to verify whether the ddio debugging of DA data is problematic.)
- 2020-06-23 04:40:02下载
- 积分：1
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led
LED灯、跑马灯的显示源程序，包括对代码的说明(Display source code LED lights, marquees, including the code specification)
- 2013-01-18 18:20:57下载
- 积分：1
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18 x 18 华莱士树乘法器
经过测试的 VHDL 代码为 18 x 18 位华莱士树乘法器
- 2022-01-30 15:01:08下载
- 积分：1
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Using VHDL realize CPLD (EMP240T100C5) of the PWM output
利用VHDL实现CPLD（EMP240T100C5）的PWM输出-Using VHDL realize CPLD (EMP240T100C5) of the PWM output
- 2022-05-27 08:17:35下载
- 积分：1
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example16-dac7512-sina-wave-ok
VHDL 基于cpld EPM570的DA转换代码(VHDL CPLD EPM570 the DA conversion code based on)
- 2014-12-08 14:02:34下载
- 积分：1
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DDS FPGA开发下的verilog源代码
DDS_AD9854_for FPGA ,FPGA开发下的verilog源代码，信号发生器(DDS_AD9854_for FPGA, verilog source code, signal generator.)
- 2013-01-14 00:13:36下载
- 积分：1
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FIRDF_design
FIR带通、带阻滤波器设计，需要输入截止频率以及容许偏差。(FIR band pass and band stop filter design)
- 2020-09-28 15:17:44下载
- 积分：1
