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writereadflash
这个是用VHDL实现FPGA对FLASH的读写。(This is achieved using VHDL FLASH FPGA to read and write.)
- 2013-07-14 22:06:38下载
- 积分:1
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下午5点的代码及说明,verilog代码,几乎所有的IC面试都会问…
5分代码及说明,verilog代码,几乎所有的IC面试都会问到这个问题,所以总结了一下发了上来,共同学习!-5 pm code and explanations verilog code Almost all the interviews will IC asked this question, summed up in the ranks about fat, learn together!
- 2022-02-21 11:34:44下载
- 积分:1
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利 用 来 vhdl 设 计 p cm的 实 现
利 用 来 vhdl 设 计 p cm的 实 现-Vhdl design used for the realization of p cm
- 2023-06-01 20:05:03下载
- 积分:1
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非常好的VHDL音乐
library ieee;
use
ieee.std_logic_1164.all;
use
ieee.std_logic_unsigned.all;
entity song is
port(clk_4MHz,clk_4Hz:in std_logic;
----预置计数器和乐谱产生器的时钟
digit:buffer std_logic_vector(6 downto 0); ----高、中、低音数码管指示
zero:out std_logic_vector(4 downto 0); ----用于数码管高位置低
- 2022-12-29 04:50:03下载
- 积分:1
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hammingaTB
Design HDL code for a circuit that calculates the Hamming distance of two 8-bit inputs.
- 2013-11-06 15:45:02下载
- 积分:1
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在vhdl开发环境下,关于协议PS2 verilog 源码
在vhdl开发环境下,关于协议PS2 verilog 源码-In VHDL development environment, with regard to the agreement PS2 verilog source code
- 2022-05-06 00:46:27下载
- 积分:1
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main
EP2C35A实验箱基于NIOSII的串行AD_DA编程(EP2C35A experimental box based NIOSII the serial AD_DA programming)
- 2013-04-22 11:18:27下载
- 积分:1
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xilinx provided on the FPGA hardware design timing constraints of the amount of...
xilinx公司提供的关于FPGA硬件设计的额时序约束参考资料-xilinx provided on the FPGA hardware design timing constraints of the amount of reference material
- 2023-06-26 19:00:04下载
- 积分:1
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M25P80 serial memory for applications Verilog program
针对串行存储器M25P80应用的verilog程序-M25P80 serial memory for applications Verilog program
- 2022-03-12 06:10:14下载
- 积分:1
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从两个小的产生更广泛的ALU
Generating a wider ALU from two small ones
- 2022-07-18 07:53:37下载
- 积分:1