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a
用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写(verilog ise divider)
- 2013-07-21 15:03:31下载
- 积分：1
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8.4-ADC0809-VHDL-control-program
基于VHDL语言，实现对ADC0809简单控制(Based on VHDL language, to achieve the ADC0809 simple control)
- 2011-11-29 08:43:07下载
- 积分：1
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QPSK_System
实现QPSK系统的调制解调仿真，基带成形滤波器采用升余弦滚降滤波器，将仿真的误码率与理论误码率作了比较(Implement QPSK modulation and demodulation simulation system, the baseband shaping filter using Raised Cosine filter will BER simulation were compared with the theoretical BER)
- 2020-12-22 15:39:07下载
- 积分：1
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Add_sub_struc
8位加减器，八位减法器与加法器，用过一个控制端可以自由变换，采用移位加法方式，用途广泛，利用减法位补码加法的理论实现。(8 addition and subtraction, eight subtractor and adder, used a control terminal can freely change the using Shift addition, a wide range of uses, the use of subtraction complement addition theory to achieve.)
- 2012-05-14 20:36:26下载
- 积分：1
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E1（一级欧洲传输标准）
E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)
- 2023-08-26 23:00:03下载
- 积分：1
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Cadence_manual_1.2.pdf
Cadence_manual_1.2.pdf
- 2022-01-26 00:20:48下载
- 积分：1
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FIR滤波器的VHDL语言实现
FIR滤波器的VHDL语言实现-The implement of FIR Filter based on VHDL
- 2022-01-24 13:17:20下载
- 积分：1
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基于VHDL的I2C程序0005,很不错的论文及程序，，大家快下啊
基于VHDL的I2C程序0005,很不错的论文及程序，，大家快下啊-based on the I2C procedures VHDL 0005, a very good paper and procedures, we quickly under ah
- 2022-03-18 17:11:42下载
- 积分：1
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vhdl coding for Carry Select Adder
这是一个vhdl代码的进位选择加法器及其工作100%。
- 2023-08-26 17:05:04下载
- 积分：1
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dpll
用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证(verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider )
- 2014-04-22 08:36:53下载
- 积分：1
