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I2C_ise9migration
说明： IIC 的Verilog实现，工程是在Xilinx的ISE9.1上实现的(IIC of the Verilog implementation project was implemented on Xilinx' s ISE9.1)
- 2010-04-02 09:26:54下载
- 积分：1
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This tutorial presents an introduction to Altera’s Nios R
II processor, which...
This tutorial presents an introduction to Altera’s Nios R
II processor, which is a soft processor that can be in-
stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor and its associated memory and peripheral components are easily instantiated by using Altera’s SOPCBuilder in conjuction with the Quartus R II software.
- 2023-06-21 11:25:02下载
- 积分：1
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de2 vga controller board can also be used for other development
de2 vga控制器，也可用于其他板子开发-de2 vga controller board can also be used for other development
- 2022-05-17 01:30:37下载
- 积分：1
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组合电路的设计8位加法器设计(ADD8.vhd)
组合电路的设计8位加法器设计(ADD8.vhd)-Combinational Circuit Design 8-bit adder design (ADD8.vhd)
- 2022-10-25 12:35:04下载
- 积分：1
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audio_verilog
AUDIO音频模块AN831的录音及播放FPGA代码，测试通过(AUDIO audio module AN831 recording and playback of FPGA code, the test passed)
- 2020-09-12 09:27:58下载
- 积分：1
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ethernet_loopback
通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation)
- 2017-11-20 10:21:38下载
- 积分：1
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verilog黄金参考指南中文版
Verilog 黄金参考指南是 Verilog 硬件描述语言及其语法 语义 合并以及将它应用到硬件设计的一个简明的快速参考指南。(Verilog Golden Reference Guide is a concise and fast reference guide for Verilog Hardware Description Language and its syntax and semantics merging and its application to hardware design.)
- 2020-06-18 04:20:02下载
- 积分：1
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sim
csapp 第二版 体系结构实验 答案 第三个部分能跑58分(the second edition csapp architecture experiment the third part of the answer can run 58 minutes)
- 2013-05-20 10:28:00下载
- 积分：1
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cf_ad9649_ebz_edk_14_4_2013_03_19.tar
说明： ad9649的fpga驱动程序,FMC接口，基于Xilinx KC705(AD9649 Evaluation Board, FMC Interposer & Xilinx KC705 Reference Design)
- 2020-06-28 14:00:02下载
- 积分：1
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AM-modulated-learning-ladder
AM modulated learning ladder
- 2015-07-15 09:42:45下载
- 积分：1
