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sync(shipintongbuxinhao)
基于QuartusII环境下以模块化的形式做成的视频复合同步信号。(QuartusII-based environment to create the form of modular composite video sync signal.)
- 2009-04-06 12:49:46下载
- 积分：1
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GPS基带处理的verilog代码
GPS软件接收机基带处理的verilog程序，通过解扩解调，同步等过程将中频数据转换为原始导航数据
- 2022-03-24 13:40:54下载
- 积分：1
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FULL-FPGA-SCH
包括Cyclone II EP2C20 原理图.CycloneII开发板原理图fpga.EP1C3T144 FPGA develop board manual.EP1C6Q240C6开发板原理图.EP2C8开发板原理图.EPM1270F256C5 MAX_II_board_schematics.SF-EP1V2+FPGA开发板原理图.XC3S400红色飓风开发板原理图.红色飓风II代开发板原理图2.(Including the Cyclone II EP2C20 schematic . CycloneII development board schematics fpga.EP1C3T144FPGA develop board manual.EP1C6Q240C6 development board schematic . EP2C8development board schematics . EPM1270F256C5MAX_II_board_schematics.SF-EP1V2+FPGA development board schematic . XC3S400red hurricane development board schematics. Red hurricane II development board schematic diagram2)
- 2012-04-28 15:47:07下载
- 积分：1
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74HC161
74ls161 基于verilog语言的实现 源程序在压缩包的hdl文件夹中(74ls161 language based on the realization of verilog source package in compressed folder hdl)
- 2020-07-01 17:00:01下载
- 积分：1
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JSFP
奇数分频-此程序对输入频率sysclk有奇数（X）分频的功能(Odd frequency- this program has an odd number of input frequency sysclk (X) frequency function)
- 2011-08-01 12:37:42下载
- 积分：1
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DE2_WEB_QII_60
ALTERA官方板子DE2官方代码，芯片是EP2C35F672C6N(ALTERA official board DE2 official code, the chip is EP2C35F672C6N)
- 2017-09-07 19:35:35下载
- 积分：1
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hulf
说明： 设计一个哈夫曼编码器
要求对一段数据序列进行哈夫曼编码，使得平均码长最短，输出各元素编码和编码后的数据序列。
① 组成序列的元素是[0-9]这10个数字，每个数字其对应的4位二进制数表示。比如5对应0101，9对应1001。
② 输入数据序列的长度为256。
③ 先输出每个元素的编码，然后输出数据序列对应的哈夫曼编码序列。(Designing a Huffman Encoder
Huffman coding is required for a data sequence to minimize the average code length and output the coded and coded data sequence of each element.
(1) The elements that make up the sequence are the 10 digits [0-9], and each digit is represented by its corresponding 4-bit binary number. For example, 5 corresponds to 0101, 9 corresponds to 1001.
(2) The length of the input data sequence is 256.
(3) First output the encoding of each element, and then output the Huffman encoding sequence corresponding to the data sequence.)
- 2019-06-19 21:49:58下载
- 积分：1
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AXI-full
axi协议中的full子协议，可用于直接访问zynq器件的ddr器件。(The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.)
- 2018-03-15 10:40:55下载
- 积分：1
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AD9764
一个AD9764的基于FPGA的驱动，希望对有需要的朋友有所帮助(An AD9764 FPGA-based drive, we want to help a friend in need)
- 2013-09-05 01:48:57下载
- 积分：1
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filter-design
MBD-FPGA数字滤波器设计基本流程,基于DSP builder(MBD-FPGA basic process of digital filter design)
- 2020-12-02 20:39:26下载
- 积分：1
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