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这是用VHDL编写的CRC32
这是利用VHDL编写的一个CRC32的代码，文档只有代码，具体原理请参考其他文献-This is the use of VHDL prepared a CRC32-code, the document is only a code Please refer to specific tenets of other literature
- 2022-12-25 21:15:08下载
- 积分：1
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update-for-the-item-CVFX-C02
This is the update firmware for CVFX-C02, 7" motorized touch screen car dvd player gps
- 2013-06-30 03:39:08下载
- 积分：1
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HDLC some relevant documents, HDLC design may be very helpful!
HDLC的一些相关文档，可能对HDLC设计有很大的帮助！-HDLC some relevant documents, HDLC design may be very helpful!
- 2022-10-21 11:55:03下载
- 积分：1
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1pps
fpga程序，产生1pps脉冲信号，使用的verilog语言。(FPGA program generates 1 PPS pulse signal, using Verilog language.)
- 2020-06-20 17:00:01下载
- 积分：1
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procedures in the report, with QuartusII operations, the attention to word from...
程序在报告中，要 用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-enter those symbols on the
- 2022-03-22 23:49:36下载
- 积分：1
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在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。...
在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。运用两个个计数器分别对PN码计数以及序列出现的次数计数。改变ＰＮ码结构可以作为通用数列检测器-QuartusII use in AHDL language, the first PN generator designed to generate a data stream 11 throughout the cycle has an effective data = 2047 re-designing the state machine used to detect the serial data stream in sequence. The use of two counters were counting on the PN code, as well as counting the number of sequences occur. Changes in the structure of PN code series can be used as general-purpose detector
- 2023-03-11 09:20:03下载
- 积分：1
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CJ2
关键词：清华大学计算机系 计算机组成原理大实验 多周期cpu工程源码，内含中断，串口，以及31个指令的实现，读写内存，控制器，ALU，寄存器，分频等模块，小作业什么的可以直接从里面摘抄，为学弟学妹造福(Keywords: Department of Computer Science Computer Composition Principle experimental multi-cycle the cpu Engineering source for the benefit of mentees)
- 2020-12-29 10:09:01下载
- 积分：1
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project_first
basys3的数字钟，可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)
- 2019-06-18 10:37:53下载
- 积分：1
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数字时钟的VHDL语言描述，具有高精度，控制性能良好
数字时钟的VHDL语言描述，具有高精度，控制性能良好-Digital Clock description of the VHDL language, with high precision and good control performance
- 2022-03-23 07:25:11下载
- 积分：1
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RC6-block-cipher-using-VHDL
VHDL implementation of RC6 encryption algorithm
Test file represent applying all zero input and all zero key
note that result is correct but bytes positions are swapped
- 2020-12-01 22:09:26下载
- 积分：1
