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DE2_115_NIOS_DEVICE_LED
DE2-115开发板LED显示测试源码，对fpga开发者提供参考(DE2-115 development board LED display test source, provide a reference for fpga developer)
- 2011-09-29 15:07:10下载
- 积分：1
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T8051
IT8051，增强版的T51，兼容DW8051核的多数端口，IO需要扩展后使用
- 2022-02-12 17:39:36下载
- 积分：1
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sigmoid_FPGA
sigmoid函数硬件实现，verilog代码及其测试用例(Sigmoid function hardware implementation, verilog code and test cases)
- 2017-05-08 20:36:04下载
- 积分：1
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adder
This the adder VHDL code, it contains input and output fild, also simulate file-adder
- 2022-06-21 18:48:32下载
- 积分：1
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基于sopc ep2c5开发板的rs232例程
基于sopc ep2c5开发板的rs232例程-On sopc ep2c5 development board rs232 routines
- 2022-02-05 03:28:05下载
- 积分：1
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DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M...
DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
- 2023-07-27 16:00:03下载
- 积分：1
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我的学习经验，一种自适应分频及分频方法的实现，很好用的哦...
我的学习经验，一种自适应分频及分频方法的实现，很好用的哦-my learning experience, an adaptive frequency-frequency method and the realization of the good, oh
- 2022-02-03 01:08:00下载
- 积分：1
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spi_hello
SPI接口测试程序，Xilinx参考设计，ML507硬件测试通过.(SPI interface test code，Xilinx reference design，tested on ML507 platform.)
- 2013-09-01 09:37:04下载
- 积分：1
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Verilog代码。注册成功，对FPGA的使用标准单元库…
verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
- 2022-04-14 16:29:39下载
- 积分：1
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PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过...
PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
- 2022-02-01 22:27:36下载
- 积分：1
