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Xilinx的FPGA开发DEMO例程，功能相对来说比较全面，适合新手参考。...
Xilinx的FPGA开发DEMO例程，功能相对来说比较全面，适合新手参考。-Xilinx FPGA development DEMO routines, function relatively comprehensive reference suitable for novice.
- 2022-02-21 21:55:12下载
- 积分：1
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a good use of the Verilog Programming cpu procedures, we must make good use of.
一个很好的利用verilog编程实现的cpu程序，一定要好好利用。-a good use of the Verilog Programming cpu procedures, we must make good use of.
- 2023-03-28 18:35:03下载
- 积分：1
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ahb2wishbone_latest.tar
AHB to Wishbone memory interface VHDL source code
- 2013-01-11 11:17:03下载
- 积分：1
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"digital circuit EDA portal
《数字电路EDA入门－VHDL程序实例》---交通灯程序例子-"digital circuit EDA portal-VHDL program examples"-- traffic lights procedures example
- 2022-02-19 21:55:09下载
- 积分：1
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-------
---- WISHBONE Wishbone_BFM IP Core----
--------
---- This file is par
---- ----
---- WISHBONE Wishbone_BFM IP Core ----
---- ----
---- This file is part of the Wishbone_BFM project ----
---- http://www.opencores.org/cores/Wishbone_BFM/ ----
---- ----
---- Description ----
---- Implementation of Wishbone_BFM IP core according to ----
---- Wishbone_BFM IP core specification document.---------
---- WISHBONE Wishbone_BFM IP Core----
--------
---- This file is part of the Wishbone_BFM project----
---- http://www.opencores.org/cores/Wishbone_BFM/----
--------
---- Description----
---- Implementation of Wishbone_BFM IP core according to----
---- Wishbone_BFM IP core specification document.
- 2022-05-26 15:36:06下载
- 积分：1
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uart766
---实现的部分VHDL 程序如下。
--- elsif clk1x event and clk1x = 1 then ---if std_logic_vector(length_no) >= “0001” and std_logic_vector(length_no) <= “1001” then -----数据帧数据由接收串行数据端移位入接收移位寄存器---rsr(0) <= rxda --- rsr(7 downto 1) <= rsr(6 downto 0) --- parity <= parity xor rsr(7) --- elsif std_logic_vector(length_no) = “1010” then --- rbr <= rsr --接收移位寄存器数据进入接收缓冲器--- ...... --- end if(--- achieve some VHDL procedure is as follows.--- Elsif clk1x event and then a clk1x = s--- if td_logic_vector (length_no))
- 2007-06-02 12:44:31下载
- 积分：1
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alu
说明： VHDL实现的算术逻辑计算单元（ALU），包括modersim测试文件，即仿真结果。(VHDL implementation of the arithmetic logic calculation unit (ALU), including modersim test file, the simulation results.)
- 2011-03-26 21:18:01下载
- 积分：1
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TCM解码，VHDL代码，是我在工作中做的工程代码，时序稳定，里面有syn以及软判决的算法，经典...
TCM解码，VHDL代码，是我在工作中做的工程代码，时序稳定，里面有syn以及软判决的算法，经典-TCM decoder, VHDL code, yes, I do work in the project code, timing stability, There are syn and soft-decision algorithm, classic!
- 2022-09-27 21:25:03下载
- 积分：1
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vhdl testbench的编写，textio的编写是一个难点，也是一个重点，而这是本人搜集的多篇关于textio的文章，同时附有简单注释!...
vhdl testbench的编写，textio的编写是一个难点，也是一个重点，而这是本人搜集的多篇关于textio的文章，同时附有简单注释!-vhdl testbench preparation, textio the preparation is a difficult, but also a focus, and this is my collection of articles on textio the article, at the same time with a simple note!
- 2022-10-01 22:10:03下载
- 积分：1
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85375524AGC
Matlab agc ʵ
- 2010-04-22 21:54:28下载
- 积分：1
