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pj2-NO.6
基于FPGA的电子密码锁设计-已在开发板上成功运行，通过老师检验。(FPGA based electronic password lock design- has been successfully developed on the development board, through the teacher inspection.)
- 2017-05-26 11:54:44下载
- 积分：1
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edc_spi_command
单片机和FPGA的通信程序，发送5个数，传输稳定，可以自行修改可一次传多个数(MCU and FPGA communication program, send five the number of stable transmission, you can modify the number may be more than one pass)
- 2013-09-14 21:09:52下载
- 积分：1
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or2a
使用vhdl语言设计一位全加器，在仪器上下载并实现LED灯的闪亮(A full adder design)
- 2013-09-26 18:24:15下载
- 积分：1
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Chapter7-Sample
SAA7113 ＦＰＧＡ开发实例，非常经典(The SAA7113 FPGA development examples, very classic)
- 2012-12-06 17:00:25下载
- 积分：1
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jiaotongled
该源码用vhdl语言制作了一个简单的交通灯，方便大家学习~~(The source vhdl language produced by a simple traffic light, facilitate learning ~ ~)
- 2010-11-20 14:44:36下载
- 积分：1
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alu
说明： VHDL实现的算术逻辑计算单元（ALU），包括modersim测试文件，即仿真结果。(VHDL implementation of the arithmetic logic calculation unit (ALU), including modersim test file, the simulation results.)
- 2011-03-26 21:18:01下载
- 积分：1
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061110061
在quartus平台下使用verilog语言编程实现简单的单流水线CPU，可以执行16条基本指令(Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions)
- 2010-05-21 20:01:16下载
- 积分：1
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or1200.tar
OpenRISC 1200 cpu with integrated patches to support ORPSOC and FuseSOC builders
- 2014-12-20 04:40:23下载
- 积分：1
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请注意： 本例的源描述包含文件类型，在学习版上不能编译及模拟， 如果您需要对此描述进行编译及模拟，请与北京理工大学 ASIC研究所联系。 另外，此例与第...
请注意： 本例的源描述包含文件类型，在学习版上不能编译及模拟， 如果您需要对此描述进行编译及模拟，请与北京理工大学 ASIC研究所联系。 另外，此例与第75例是同一个电路的不同部分的描述，可以 一起参考这两个例子的描述。-Please note : The cases include the description of the source file type, version of the study can not be compiled and simulation, if you need to compile this description and simulation, Beijing Polytechnic University and the Institute of ASIC link. Additionally, the cases of 75 cases with the first of a circuit with the different parts of the description, reference together two examples of this description.
- 2022-06-30 03:50:17下载
- 积分：1
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VHDL language design stopwatch, timer function of the realization, the realizati...
VHDL语言设计的秒表，实现计时功能，实现报时功能，并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.
- 2022-09-16 02:55:02下载
- 积分：1
