有很多例子及测试代码，对初学者很有帮助，很容易上手-a lot of examples and test code, useful for beginners, it is easy to get started

isa总线接口，可以实现与isa总线　的IO和MEMERY接口(isa bus interface can be achieved with the isa bus IO interfaces and MEMERY)

NCO的VHDL程序，是利用IP核生成的，超好的，快下吧-NCO of the VHDL process is the use of nuclear-generated IP, super good, fast, are you

vhdl设计事例,有助于FPGA初学着,High-Performance 1024-Point Complex FFT-vhdl design examples, to help novice FPGA. High-Performance 1024-Point Complex FFT

Based on SVPWM three-level inverter matlab simulation, It describes the application of load forecasting, EULER numerical analysis method.

Advanced FPGA Design - Architecture, Implementation, and Optimization(Advanced FPGA Design- Architecture, Implementation, and Optimization)

硬件描述语言,verilog HDL,实现了解码器的设计-hardware description language, verilog HDL, the decoding of Design

说明：  bnn-fpga是FPGA上CIFAR-10的二进制神经网络（BNN）加速器的开源实现。 加速器针对低功耗嵌入式现场可编程SoC，并在Zedboard上进行了测试。 在编写CIFAR-10测试集中的10000张图像时，错误率是11.19％。(bnn-fpga is an open-source implementation of a binarized neural network (BNN) accelerator for CIFAR-10 on FPGA. The architecture and training of the BNN is proposed by Courbarieaux et al. and open-source Python code is available. Our accelerator targets low-power embedded field-programmable SoCs and was tested on a Zedboard. At time of writing the error rate on the 10000 images in the CIFAR-10 test set is 11.19%.)

quartus 中，高级io分配，手动的例子-Quartus senior io distribution, manual example

this is the vhdl code for the arithmetic logic unit.enjoy!