-
VCS_labs
说明： EDA软件VCS学习中用到的实际例子，都已经通过调试验证(Practical examples used in the learning of EDA software VCS have been verified by experiments.)
- 2019-04-29 11:45:52下载
- 积分：1
-
基于Verilog的IIC协议的实现
用Verilog代码来实现iic协议，主要是通过两个按键来控制读写命令，读取的数据最后用数码管显示出来，代码里面有很详细的注释和说明。
- 2022-04-25 01:39:18下载
- 积分：1
-
MP3-coder
In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder.
Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read the output or input 576 frequency lines.(This folder contains three directories: Huffman, IMDCT and Filterbank, each of them
includes all the VHDL source codes of the component.)
- 2013-08-06 15:40:24下载
- 积分：1
-
jesd204_0_ex
说明： jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)
- 2020-11-26 14:49:31下载
- 积分：1
-
DAC0832VHDL
DAC0832 接口电路程序.功能：产生频率为762.9Hz的锯齿波DAC0832VHDL程序与仿真(DAC0832 procedures interface circuit. Functions: generate the sawtooth frequency of 762.9Hz and simulation procedures DAC0832VHDL)
- 2020-11-28 12:59:31下载
- 积分：1
-
pinlvji
verilog 简易频率计的设置，包括整个工程(verilog simple frequency meter settings, including the entire project)
- 2013-08-18 09:53:52下载
- 积分：1
-
55593397xapp592
GTH 和SMPTE IP 实现 SDI视频接收(SDI Video Receiving Based on GTH and SMPTE IP)
- 2019-02-18 16:09:33下载
- 积分：1
-
RobustVerilog_free1.2_win
RobustVerilog生成verilog工具(RobustVerilog version)
- 2021-01-22 18:18:41下载
- 积分：1
-
iq_balance
调整iq幅度不平衡的模块，可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)
- 2021-04-23 17:48:47下载
- 积分：1
-
interpolate4
调制信号后4倍内插的verilog代码，用于基带成型滤波器输入数据(4 times after modulation signal interpolation verilog code, used to baseband shaping filter input data)
- 2017-04-20 15:52:09下载
- 积分：1
