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suijitu
matlab随即图设计程序,应该比较有用,希望能申请会员成功吧。。(matlab then drawing design program)
- 2013-04-25 10:49:07下载
- 积分:1
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1、 利用FLEX10的片内RAM资源,根据DDS原理,设计产生正弦信号的各功能模块和顶层原理图; 2、 利用实验板上的TLC7259转换器,将1中得到的正弦信...
1、 利用FLEX10的片内RAM资源,根据DDS原理,设计产生正弦信号的各功能模块和顶层原理图; 2、 利用实验板上的TLC7259转换器,将1中得到的正弦信号,通过D/A转换,通过ME5534滤波后在示波器上观察; 3、 输出波形要求: 在输入时钟频率为16KHz时,输出正弦波分辨率达到1Hz; 在输入时钟频率为4MHz时,输出正弦波分辨率达到256Hz; 4、 通过RS232C通信,实现FPGA和PC机之间串行通信,从而实现用PC机改变频率控制字,实现对输出正弦波频率的控制。-a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D/A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.
- 2022-01-25 19:12:14下载
- 积分:1
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verilog-SPI-core
用VerilogHDL写的spi 核的例子(A simple example of SPI core using Verilog HDL)
- 2011-08-31 20:37:07下载
- 积分:1
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Using FPGA realize DDS, can be frequency, amplitude from hardware to complete
用FPGA实现DDS,可变频,幅值由硬件完成-Using FPGA realize DDS, can be frequency, amplitude from hardware to complete
- 2022-04-02 05:52:39下载
- 积分:1
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01_test
说明: FPGA测试程序,仅供测试硬件是否能够运行,主要功能是点亮运行指示灯(The main function of the test program of FPGA is to light the running indicator.)
- 2019-06-20 03:21:28下载
- 积分:1
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20181060261-李康_3
说明: 秒表的实现,有暂停清零功能,Quartus II(Stopwatch realization, has the pause clear function)
- 2020-12-26 15:56:03下载
- 积分:1
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alu
this is the vhdl code for the arithmetic logic unit.enjoy!
- 2013-08-22 18:51:35下载
- 积分:1
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二进制BCD码变换器采用VHDL
这是一个经过测试和使用的VHDL代码,用于将16位二进制输入数据转换为4位BCD。如果您直接驱动显示器而不经过处理器,并且希望显示在主程序中计算的参数,则该程序非常有用。有关转换的戏剧方面,请阅读随附的pdf。
- 2022-09-26 04:05:02下载
- 积分:1
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uart
用veriolg 语言编写的串口通讯程序,通过FPGA控制串口的通讯。(a veriog program completed on FPGA to contrlo a uart to communicaton with a computer )
- 2010-08-16 10:41:03下载
- 积分:1
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DDR2 SDRAM仿真模型,适合于ModelSim下工作,请先阅读readme
DDR2 SDRAM仿真模型,适合于ModelSim下工作,请先阅读readme-DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.
- 2022-02-25 20:23:26下载
- 积分:1