-
Quartus senior io distribution, manual example
quartus 中，高级io分配，手动的例子-Quartus senior io distribution, manual example
- 2022-07-11 02:00:46下载
- 积分：1
-
fsm
有限状态机工作原理、设计方法、步骤等精要说明(Finite state machine working principle, design method, such as Essentials of steps to explain)
- 2010-02-13 17:46:25下载
- 积分：1
-
uart
用Verilog HDL，实现的FPGA串口调试程序，已经在硬件上调试成功(With Verilog HDL, FPGA serial debugger implemented in hardware debugging has been successful)
- 2015-07-23 15:24:12下载
- 积分：1
-
用VHDL语言实现的LDPC码的硬件语言实现，对比验证…
用VHDL语言编写的LDPC码硬件实现语言，相对于verilog的，比较简单-Using VHDL language LDPC code hardware implementation language, compared to Verilog, and relatively simple
- 2023-05-19 11:55:03下载
- 积分：1
-
8位十六进制频率计设计 根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号；1s计数结束后，计数值被锁入锁存器，计...
8位十六进制频率计设计 根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号；1s计数结束后，计数值被锁入锁存器，计数器清零，为下一测频计数周期做好准备。测频控制信号可由一个独立的发生器（FTCTRL）来产生。-8-bit hexadecimal Cymometer designed in accordance with the definition of frequency and frequency of the basic principles of measurement to determine the frequency of the signal must have a pulse width of the input signal for 1s permit pulse counting signal 1s counting after the total value was locked into the lock depositors, counters cleared for the next count cycle frequency measurement ready. Frequency control signal generator may be an independent (FTCTRL) to generate.
- 2022-06-19 17:20:21下载
- 积分：1
-
一款8位Turbo
一款8位Turbo-51的CPU软核的设计-An 8 Turbo-51" s soft-core CPU design ....
- 2022-02-25 13:52:11下载
- 积分：1
-
AT89C51-DPSK
基于单片机和FPGA实现DPSK调制解调的功能和分类比较。(MCU and FPGA implementation based on DPSK modulation and demodulation functions and classification comparison.)
- 2011-01-06 19:16:16下载
- 积分：1
-
VHDL硬件描述语言与数字逻辑电路设计
VHDL硬件描述语言与数字逻辑电路设计-VHDL hardware description language and digital logic circuit design
- 2023-03-10 23:05:04下载
- 积分：1
-
ADV7180
files describe how to configure an ADV7180
- 2010-03-17 22:49:23下载
- 积分：1
-
sqrt_pipeline
说明： Matlab - to hdl code for square root
- 2020-06-17 12:20:02下载
- 积分：1
