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PLD与8051接口的参考设计 Xilinx提供的verilog源代码
PLD与8051接口的参考设计 Xilinx提供的verilog源代码-PLD 8051 interface with the Xilinx Reference Design for the Verilog source code
- 2022-05-12 14:58:28下载
- 积分:1
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reg_counter
时钟输入:在每个时钟的正沿或负沿对数据进行处理 联合开发网 - pudn.com
- 2008-05-29 19:47:35下载
- 积分:1
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Uart2Sdram2TFT_RGB2GRAY
说明: 使用FPGA实现RGB图像转灰度图像的算法,下载入自己的电路板可直接将摄像头拍摄到的图像实时转换成灰度图像(FPGA is used to realize the algorithm of transforming RGB image into gray image. The image captured by the camera can be converted into gray image in real time by downloading it into its own circuit board)
- 2019-12-30 19:42:58下载
- 积分:1
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Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compe...
Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compensation Filter v6.1
- 2022-02-02 23:02:14下载
- 积分:1
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SDC_RDC
基于FPGA的双通道旋转变压器测角系统硬件设计,分析的比较清楚。(FPGA based dual channel rotary transformer angle measurement system hardware design, analysis of the relatively clear.)
- 2011-08-07 20:23:10下载
- 积分:1
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audio_verilog
AUDIO音频模块AN831的录音及播放FPGA代码,测试通过(AUDIO audio module AN831 recording and playback of FPGA code, the test passed)
- 2020-09-12 09:27:58下载
- 积分:1
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这是一本关于VHDL编程的书籍,网上突然发现的,相信对相关人员会有所用途....
这是一本关于VHDL编程的书籍,网上突然发现的,相信对相关人员会有所用途.-This is a book on VHDL programming, on-line suddenly found, I believe that the relevant staff will be use.
- 2023-02-06 08:50:07下载
- 积分:1
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avaloncsequencer
a sequence generator
- 2009-07-27 20:59:09下载
- 积分:1
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内嵌BRAM设计LIFO堆栈
具有先进后出的堆栈功能。此LIFO堆栈具有两个按键(write, read),按下write键后,开始输入数据data0-data3;按下read键后,7段数码管开始倒序显示data3-data0(十进制)。
高级要求(可选): 按下write键,VGA显示“Write”字样,并同时显示输入数据;按下read键,VGA显示“Read”字样,并同时显示输出数据。
- 2022-04-29 13:49:12下载
- 积分:1
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xilinx 开发板程序,LED灯控制程序
xilinx 开发板程序,LED灯控制程序-Xilinx development board procedures, LED lamp control procedures
- 2022-08-08 23:14:07下载
- 积分:1