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can总线
说明： SJA1000的ip核和相关测试脚本,OPENCORES 下载(SJA1000 IP downloads from opencores)
- 2019-11-15 10:07:14下载
- 积分：1
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Modulation
产生长度为100的随机二进制序列
发送载波频率为10倍比特率，画出过采样率为100倍符号率的BPSK调制波形（前10个比特） ，及其功率谱
相干解调时假设收发频率相位相同，画出x(t) 的波形，假设低通滤波器的冲激响应为连续10个1（其余为0），或连续12个1 （其余为0） ，分别画出两种滤波器下的y(t)，及判决输出（前10个比特）
接收载波频率为10.05倍比特率，初相位相同，画出x(t) 的波形，假设低通滤波器的冲激响应为连续10个1，画出两种滤波器下的y(t)，及判决输出（前20个比特）
采用DPSK及延时差分相干解调，载波频率为10倍比特率，画出a, b, c, d点的波形（前10个比特）
DPSK及延时差分相干解调，载波频率为10.25倍比特率时，画出a, b, c, d点的波形（前10个比特）
DPSK及延时差分相干解调，载波频率为10.5倍比特率时，画出a, b, c, d点的波形（前10个比特）
(Produce random binary sequence of length 100
The transmission carrier frequency is 10 times the bit rate, draw a sampling rate of 100 times the symbol rate of the BPSK modulation waveform (first 10 bits), its power spectrum
Coherent demodulation of assuming the same as the phase of the transmitting and receiving frequencies, and draw the waveform x (t), assuming that the impulse response of the low pass filter 10 consecutive 1 (the remainder is 0), or 12 consecutive 1 (the remainder is 0), y (t) is drawn under the two filters respectively, and the decision output (10 bits)
The received carrier frequency is 10.05 times the bit rate, the same initial phase, draw the waveform x (t), assuming that the impulse response of the low pass filter of 10 consecutive 1, shown under two filter y (t), and decision output (20 bits)
DPSK and delay differential coherent demodulation, the carrier frequency is 10 times the bit rate, draw a, b, c, d point of the waveform (first 10 bits)
DPSK and delay)
- 2020-12-14 08:19:14下载
- 积分：1
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FPGA-based--DC-speed-controller
针对某船舶模型定位系统中调速电机，以FPGA(现场可编程门阵列)为控制器，采用数字比例积分调节器实现电机的速度控制算法，设计出数字化调速控制器(Positioning system for a ship model in the motor speed, the FPGA (field programmable gate array) for the controllers, proportional integral regulator with digital speed of the motor control algorithm, designed digital speed controller)
- 2011-05-17 15:50:57下载
- 积分：1
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quartus-ii-automatically-assign-pins
quartus ii 中自动分配管脚的三种方法(quartus ii automatically assign pins are three ways)
- 2012-03-31 17:12:54下载
- 积分：1
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telephone-cost-metering
该程序用来实现电话计时以算取费用，比较简单(telephone cost metering verilog code)
- 2013-11-03 19:45:00下载
- 积分：1
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VHDL language is designed to be simple to use the CPU, the focus of the design o...
用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the final design of the micro-operation microinstruction to verify the correctness of the design. Can achieve the basic add, subtract, multiply, divide, transfer, recycling and other operations.
- 2022-01-26 04:06:25下载
- 积分：1
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伺服电机控制
伺服电机
RC 伺服电机是的电机的位置可以从外部控制的一种。他们是小巧、 紧凑而且相当便宜。所以他们大多用在机器人项目。轴的旋转角度是限于 270 度左右。
典型的 RC 伺服有三个连接。
黑色： Gnd
红色： 电源 (5 VDC)
白色： 控制销 （PWM）
请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报
- 2022-05-29 22:19:02下载
- 积分：1
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这是一个在Quartus II软件中编写的vhdl程序。程序下载后可用蜂鸣器播放音乐...
这是一个在Quartus II软件中编写的vhdl程序。程序下载后可用蜂鸣器播放音乐 -This is a Quartus II software in the preparation of the VHDL program. After the buzzer can be used to download music player
- 2022-06-14 11:30:29下载
- 积分：1
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tr_wave
FPGA编写的三角波发生器，可以产生100HZ～500KHZ以上的三角波，波形稳定(FPGA prepared triangular wave generator, can produce more than 100HZ ~ 500KHZ triangle wave, waveform stability)
- 2007-08-25 03:15:38下载
- 积分：1
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豪华的CPU的VHDL代码的大学
DLX CPU VHDL CODE UNIVERSITY
- 2022-05-06 01:12:25下载
- 积分：1
