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LEDTest2
This is a running 10 bit led on VHDL code including switch to shift from increasing or decreasing
- 2017-10-28 16:27:20下载
- 积分：1
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Source code for asyn_fifo using verilog language.
异步FIFO 设计源代码，内涵完整的verilog源代码和测试代码。-Source code for asyn_fifo using verilog language.
- 2022-04-14 15:20:53下载
- 积分：1
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频率计，ＶＥＲＩＬＯＧ代码，含详细 中文注释．
频率计，ＶＥＲＩＬＯＧ代码，含详细 中文注释．-Cymometer, VERILOG code, containing a detailed Chinese Notes.
- 2023-05-22 17:20:02下载
- 积分：1
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CCPRRIzipP
一种基于CPRI标准的WCDMA NoddeB射频光纤拉远接口FPGA设计.pdf
(CPRI compliant the WCDMA NoddeB RF fiber pull far from the interface of the FPGA design. Pdf)
- 2012-07-19 22:29:39下载
- 积分：1
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simpleCpu
relative cpu design implementation
- 2013-08-14 21:22:39下载
- 积分：1
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snake_VHDL
基于vhdl编写的贪吃蛇游戏，课程设计必备(Based on the VHDL language of the snake game, curriculum design essential)
- 2020-11-06 09:49:50下载
- 积分：1
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TCM_Modulation
TCM编码的调制端，采用8PSK，2/3码率的卷积码的matlab程序(TCM coded modulation client, using 8PSK, 2/3 code rate of convolutional codes of matlab program)
- 2021-04-20 00:08:51下载
- 积分：1
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9_ImageMorphologic
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像形态学部分,腐蚀,膨胀,细化算法(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image morphology section, corrosion, swelling, thinning algorithm)
- 2020-10-23 17:17:22下载
- 积分：1
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VLSI-Paper
VLSI based question set
- 2013-04-02 18:36:26下载
- 积分：1
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学习使用HDL Bencher生成测试积累，并直接调用ModelSim进行仿真的方法....
学习使用HDL Bencher生成测试积累，并直接调用ModelSim进行仿真的方法.-learning HDL Bencher generate test accumulation, and called directly ModelSim simulation methods.
- 2022-02-28 22:36:00下载
- 积分：1
