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the program have designed a PCM signal timing modules, including the CLK input,...
该程序设计了一个产生PCM码流时序信号的模块，他包括输入端CLK，SET及输出端Q1,Q2,Q3-the program have designed a PCM signal timing modules, including the CLK input, and output SET Q1, Q2 and Q3
- 2022-02-15 04:03:30下载
- 积分：1
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verilog code for counter four
verilog code for counter four
- 2022-01-26 05:32:56下载
- 积分：1
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递增方式在4位数码管上向上计数显示从0000
递增方式在4位数码管上向上计数显示从0000-0001->0002……..9999….0000….0001….
-- 利用CPLD设计了一个4位十进制计数器，并用数码管显示当前计数值-Incremental approach in the four counts upward digital tube display from 0000-0001-
- 2022-11-11 14:10:03下载
- 积分：1
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ov7620的CPLD采集程序，VHDL语言
ov7620的CPLD采集程序，VHDL语言-ov7620 CPLD acquisition procedures, VHDL
- 2022-10-29 18:00:04下载
- 积分：1
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Decodificador
System Verilog decodificator.
Enters a value(binary), drops hundreds, tens and units in BCD
- 2013-05-15 02:11:45下载
- 积分：1
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CCD
对ccd图像进行解码采集，并通过VGA输出(Ccd image decoding of the collection, and through the VGA output)
- 2009-07-16 22:35:30下载
- 积分：1
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report
说明： report for a report for a class
- 2019-04-17 21:19:15下载
- 积分：1
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sawtooth-waveform
在ＦＰＧＡ中产生的频率可调的锯齿波型信号发生器(The frequency of the FPGA to generate the sawtooth waveform signal generator adjustable)
- 2011-08-01 08:54:11下载
- 积分：1
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I2C控制核设计,由VHDL语言编写,使普通I/O端口实现I2C性能
I2C控制核设计,由VHDL语言编写,使普通I/O端口实现I2C性能-I2C control of nuclear design, VHDL language, I/O ports I2C Performance
- 2023-04-17 20:45:02下载
- 积分：1
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Verilog
Verilog-HDL程序设计实用教程收集，内容丰富，设计技巧多样。-Verilog-HDL Design Tutorial practical collection, rich in content and variety of design skills.
- 2022-08-25 02:18:46下载
- 积分：1
