-
10进制计数器的VHDL描述必须实验
10进制计数器,VHDL描述的,实验必备-10 hexadecimal counters, VHDL description of the experiment must
- 2022-03-17 18:09:21下载
- 积分:1
-
submodule
verilog 双模块算术平均值计算模块,子模块在时钟上升沿技术,高层模块根据当前计数值计算算数平均(verilog double module arithmetic mean calculation module, sub-module in the clock rising edge technology, high-level module is calculated based on arithmetic average of the current count)
- 2011-01-05 22:49:16下载
- 积分:1
-
from across the Xilinx website, learning some FPGA dynamic reconfigurable good e...
从Xilinx网站上下的,学习FPGA部分动态重配置很好的例子。-from across the Xilinx website, learning some FPGA dynamic reconfigurable good example.
- 2023-03-28 16:10:04下载
- 积分:1
-
出租车记价器,使用vhdl语言编写的源码及其仿真。
出租车记价器,使用vhdl语言编写的源码及其仿真。-Taxi price of devices in mind, use the source code written in vhdl and simulation.
- 2022-03-06 03:11:59下载
- 积分:1
-
classdiagramnew
class diagram diagram for AIRS
- 2015-06-10 22:44:10下载
- 积分:1
-
Altra Inc. bought a Max II EPM1270T144 circuit board, one written in Verilog HDL...
买的Altra公司的一款Max II EPM1270T144的电路板,其中的一个用Verilog HDL 编写的驱动数码管的程序,完全可用。-Altra Inc. bought a Max II EPM1270T144 circuit board, one written in Verilog HDL using the digital controls process-driven, fully available.
- 2022-02-16 01:33:54下载
- 积分:1
-
Based on the VHDL language for selecting the three sequences, you can have a cyc...
基于VHDL语言的3级序列的产生,可以循环产生周期为7的m序列
-Based on the VHDL language for selecting the three sequences, you can have a cycle for cycle 7 m sequence
- 2023-08-16 17:00:04下载
- 积分:1
-
vhdl source code for 8 bit datapath logic
vhdl source code for 8 bit datapath logic
- 2022-07-04 04:52:16下载
- 积分:1
-
VHDL的初学者可以参考此VHDL加法器,相信会给你带来不小的收获...
VHDL的初学者可以参考此VHDL加法器,相信会给你带来不小的收获-VHDL beginner can refer to the VHDL adder, I believe will bring you not a small harvest
- 2022-05-20 03:51:48下载
- 积分:1
-
ADAPTIVEFILTER
采用vhdl代码描述自适应滤波器,具有很好的可参考性,和实用性(Vhdl code to describe the use of adaptive filter, can be found with a good nature and usefulness of)
- 2010-02-05 23:37:48下载
- 积分:1