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实现
Implementation of
Image Processing Algorithms in FPGA Hardware.
- 2023-02-08 15:20:04下载
- 积分：1
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fpga——实现led灯不同变化控制
这是一段写pwm的硬件程序，通过不同的占空比控制不同led灯的亮度，这样可以很好地体现vhdl的硬件代码的优点，
- 2022-04-12 04:33:17下载
- 积分：1
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SimpleVOut-master
说明： SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals
in various formats. The cores connect using AXI-streams. Most configurations
(resolution, framerate, colordepth, etc.) are set at compile-time using
Verilog parameters. See svo_defines.vh for details on those parameters.
- 2020-06-24 21:20:01下载
- 积分：1
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数字频率计
说明： 设计一简易数字频率计，其基本要求是：
1)测量频率范围0～999999Hz；
2)最大读数999999HZ,闸门信号的采样时间为1s；.
3)被测信号可以是正弦波、三角波和方波；
4)显示方式为6位十进制数显示；
5）具有超过量程报警功能。
5)输入信号最大幅值可扩展。
6）测量误差小于+-0.1%。
7)完成全部设计后，可使用EWB进行仿真，检测试验设计电路的正确性。(The basic requirements of designing a simple digital frequency meter are:
1) The measuring frequency range is 0-999999 Hz.
2) The maximum reading is 999999HZ, and the sampling time of gate signal is 1 s.
3) The measured signal can be sine wave, triangle wave and square wave.
4) The display mode is 6-bit decimal number display.
5) It has alarm function beyond range.
5) The maximum amplitude of input signal can be expanded.
6) The measurement error is less than +0.1%.
7) After completing all the design, EWB can be used to simulate and test the correctness of the circuit.)
- 2019-06-20 12:47:51下载
- 积分：1
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BIT
说明： FPGA应用状态机版，适合初学者学习状态机三段式，ASMD图的理解和翻译，以及Verilog语言的应用 最后对仿真的一些理解 其中包含HDL设计及testbench描述
根据要求设计了一个能求出一个32bit字中两个相邻0之间最大间隙的电路。(FPGA application state machine version, suitable for beginners to learn state machine three-stage, ASMD chart understanding and translation, and Verilog language application. Finally, some understanding of simulation, including HDL design and testbench description
According to the requirements, a circuit is designed to find the maximum gap between two adjacent zeros in a 32 bit word.)
- 2020-04-28 15:57:34下载
- 积分：1
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uart_byte_rx
说明： libero soc工程，实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)
- 2020-06-21 09:20:01下载
- 积分：1
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VHDL实现PI调节的算法。内部使用整数计算，避开了浮点数的运算。仿真结果正确...
VHDL实现PI调节的算法。内部使用整数计算，避开了浮点数的运算。仿真结果正确-VHDL realize PI regulator algorithm. Internal use integer calculations to avoid the floating point arithmetic. The simulation results correctly
- 2022-02-05 16:23:16下载
- 积分：1
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Verilog module containing a synthesizable CRC function
//* polynomial: (0 1 8)...
Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 8)
// * data width: 8-Verilog module containing a synthesizable CRC function
//* polynomial: (0 1 8)
//* data width: 8
- 2022-08-18 21:19:43下载
- 积分：1
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encoding-decoding
卷积码编码译码程序以及其modelsim仿真波形文件等(Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file)
- 2020-12-27 20:59:03下载
- 积分：1
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P4 (3)
支持{addu、subu、lui、ori、jal、jr、lw、sw、nop}指令集的单周期CPU，verilog硬件描述语言实现(Support {addu, subu, lui, ori, jal, jr, lw, sw, nop} instruction set of one-cycle CPU, Verilog hardware description language implementation)
- 2018-12-02 17:22:40下载
- 积分：1
