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AN66806
提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码(Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code)
- 2013-08-13 14:42:55下载
- 积分：1
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Tutorijal 6
Ovo sto saljem je tutorijal 7 sa vhdlom
- 2018-12-22 06:47:31下载
- 积分：1
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简易数字信号分析仪（眼图）
采用VHDL语言编写，此题为全国大学生电子设计竞赛题目，产生一个伪随机信号，并用时钟提取模块提取时钟，最终能在示波器上获得眼图，验证实验结果。此程序已经经过本人亲自验证，完全可用，可用于电赛培训之中。
- 2022-07-22 14:59:00下载
- 积分：1
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VHDL数字系统设计和工程实践6，包含原理，真值表和原理图，以及VHDL源代码....
VHDL数字系统设计和工程实践6，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice, six, including the principles, truth table and schematic, as well as VHDL source code.
- 2022-08-03 02:10:09下载
- 积分：1
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Simple I2C controller
Simple I2C controller
-- 1) No multimaster
-- 2) No slave mode
-- 3) No fifo s
--
-- notes:
-- Every command is acknowledged. Do not set a new command before previous is acknowledged.
-- Dout is available 1 clock cycle later as cmd_ack
-Simple I2C controller-- 1) No multimaster-- 2) No slave mode-- 3) No fifo"s---- notes :-- Every command is acknowledged. Do not set a ne w command before previous is acknowledged.-- D is available out a clock cycle later as cmd_ack
- 2023-03-08 10:05:03下载
- 积分：1
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Advanced FPGA
Design
Architecture, Implementation,
and Optimization
Advanced FPGA
Design
Architecture, Implementation,
and Optimization
- 2022-02-05 23:31:15下载
- 积分：1
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imports
displayport 参考设计，可以对比自己工程做验证，另有参考设计XAPP1178未找到，采用方案为DP159 + Artix7 FPGA(xilinx displayport sink design)
- 2021-01-11 16:58:50下载
- 积分：1
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八路AD采集adc128s022
FPGA AD采集八路数据，12位分辨率，小梅哥FPGA的开发程序，实测可用(FPGA AD collects eight path data, 12 bit resolution, and the development program of Mayo FPGA.)
- 2020-12-17 16:59:11下载
- 积分：1
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clk_generator
时钟分频代码，PWM产生 RTL 源代码。(clock divider，PWM generator RTL Source Code)
- 2013-08-18 09:29:42下载
- 积分：1
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CameraTrackingmaster
moving tracking based in D5M camera
tracking camera
- 2016-04-08 14:57:11下载
- 积分：1
