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带load、clr等功能的寄存器
带load、clr等功能的寄存器-belt load, the function clr Register
- 2022-06-20 10:15:42下载
- 积分:1
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design a module from a trip data flow channeling Lane detected bitstream "1...
设计一个模块,从一个窜行数据流里检测出码流“11100”,这个模块包括reset,clk,datain及输出端pmatch-design a module from a trip data flow channeling Lane detected bitstream "11100", this module includes reset, clk, datain and output pmatch
- 2022-07-06 13:42:26下载
- 积分:1
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GAL
有关gal器件的编程入门,以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)
- 2013-07-09 22:50:01下载
- 积分:1
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This is what I did do a UART transmitter when the source and hope for all of us.
这是我做UART时候做的一个发送器的源码,希望对大家有用。-This is what I did do a UART transmitter when the source and hope for all of us.
- 2022-03-25 00:51:09下载
- 积分:1
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based on VHDL development of the I486 bus interface procedures. Implementation o...
基于VHDL语言开发的I486总线接口程序。实现了一个三态的总线,可保证数据的正常传输。-based on VHDL development of the I486 bus interface procedures. Implementation of a three-state bus can ensure that the normal data transmission.
- 2023-05-12 23:40:03下载
- 积分:1
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A4_Uart_Top
串口! 这是一个使用的通信程序 , 非常好用。(serial port Serial port! This is a communication program used, very useful.)
- 2020-06-17 14:00:01下载
- 积分:1
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fpga数码管显示
让你EJ疼没人开门吗维护和输入热火男的竟然也可以看看一份心疼你身边女人很多好的主人你让他愤怒和难题太难太难太难输入你的人难道她和他人的烦恼的童年听到她赫然发红包少年人反而能认识的男人的法人俄方的人体内
- 2023-01-03 09:40:17下载
- 积分:1
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sin
基于单片机的DDS数字信号发生器设计,可以产生正弦波。三角波等(Design of DDS digital signal generator based on MCU, can produce sine wave. Triangular wave)
- 2013-04-03 18:24:00下载
- 积分:1
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2路视频光端机的,VHDL源码,使用全FPGA芯片的硬件,内建成帧、时钟、SERDES...
2路视频光端机的,VHDL源码,使用全FPGA芯片的硬件,内建成帧、时钟、SERDES-2-way video PDH" s, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
- 2022-07-17 15:40:45下载
- 积分:1
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5956474temperature
DS18b20 temperature sensor vhdl code
- 2010-07-04 03:46:44下载
- 积分:1