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Verilog语言手册
Verilog Language Manual
- 2022-04-19 20:28:43下载
- 积分:1
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SD_verilog
说明: 该代码,只用了硬件描述语言Verilog在完成对SD卡控制器的编写,经济实用(The code, only the hardware description language Verilog in the completion of the SD card controller to prepare, economical and practical)
- 2020-12-27 22:19:02下载
- 积分:1
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PWM_usingENCODE
FPGA Boards - Spartan 3 E Starter Kit
- 2017-07-19 14:55:21下载
- 积分:1
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Xilinx V5 FPGA详细规格、编程FPGA参考,系统设计…
detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.
- 2022-03-16 03:52:38下载
- 积分:1
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fpga_2014_flappy_bird
用VHDL语言写了个FLAPPY_BIRD的程序,利用板子与屏幕可以运行游戏(VHDL language to write a program FLAPPY_BIRD by the board and the screen can run the game)
- 2020-11-06 09:59:49下载
- 积分:1
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FSM
It is the FSM implemented in Xylinx 14.7 on FPGA
- 2015-09-28 15:50:09下载
- 积分:1
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fir48
48阶FIR设计,采用VHDL语言描述,门级映射……(48-oders FIR design with VHDL language and gate level)
- 2021-04-14 19:38:55下载
- 积分:1
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基于DDS的DA正弦波输出
Sample behavioral waveforms for design file sin_rom.vThe following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design sin_rom.v. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 3F0, 3F1, 3F2, 3F3, ...). The design sin_rom.v has one read port. The read port has 1024 words of 10 bits each. The output of the read port is unregistered. Fig. 1 : Wave showing read operation. The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until
- 2022-01-26 04:06:16下载
- 积分:1
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数码管显示有片选 模块
四输入,与其他模块相连即可使用
数码管显示有片选 模块
四输入,与其他模块相连即可使用-digital film of the election showed that four input modules, and other modules can be linked to the use of
- 2022-08-24 22:54:51下载
- 积分:1
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fpga_pid
在FPGA内使用PID算法反馈控制小车速度和方向,四电机独立(PID algorithm within the FPGA using feedback control the car speed and direction, four independent motors)
- 2015-05-11 10:05:53下载
- 积分:1