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A complete signal test procedures, the various indicators of signal integrity te...
一个完整的信号测试程序,对信号的各项指标进行完整的测试,并分析-A complete signal test procedures, the various indicators of signal integrity testing, and analysis of
- 2022-03-23 02:41:40下载
- 积分：1
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希尔伯特变换是通信系统中的一个重要组成部分，如：
The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented.
The detailed discussion can be found in "Digital Hilbert Transformers or FPGA-based Phase-Locked Loops" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940).
The design is fully pipelined for maximum throughput.
- 2023-02-02 09:20:04下载
- 积分：1
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adc_dac
ADC-DAC transmittion works thru SPI on 25 MHZ. Used for some student project on Xilinx sprtan3a FPGA
- 2016-12-01 19:44:33下载
- 积分：1
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MIT_Press_Circuit_Design_with_VHDL_(2004)
circuit design with VHDL e-book MIT Press....
- 2009-05-08 00:33:54下载
- 积分：1
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exercise3
用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分：1
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基于FPGA的DDS
基于FPGA的DDS。可以产生三种波形：正弦，方波，三角波。频率分辨率0.012Hz。频率从0至25MHz任意可调。(FPGA-based DDS. Can produce three waveforms: sine, square, triangle wave. Frequency resolution 0.012Hz. Frequency is adjustable from 0 to 25MHz.)
- 2013-08-05 07:06:22下载
- 积分：1
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VC707_MIG_DDR3
说明： VC707_MIG_DDR3.sim文件夹中是仿真的文件：testbench和DDR3模型参数
VC707_MIG_DDR3.srcs文件夹中是源文件，包含DDR3的控制、收发模块、顶层文件(VC707_ MIG_ In ddr3.sim folder are simulation files: testbench and DDR3 model parameters
VC707_ MIG_ Ddr3.srcs folder is the source file, including DDR3 control, transceiver module, top-level file)
- 2020-10-16 19:20:53下载
- 积分：1
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用VHDL语言实现的LDPC码的硬件语言实现，对比验证…
用VHDL语言编写的LDPC码硬件实现语言，相对于verilog的，比较简单-Using VHDL language LDPC code hardware implementation language, compared to Verilog, and relatively simple
- 2023-05-19 11:55:03下载
- 积分：1
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用VHDL语言设计四位全加器，有低位进位和高位进位。
用VHDL语言设计四位全加器，有低位进位和高位进位。-VHDL language with four full-adder design, there are low and the high binary binary.
- 2022-03-20 15:03:38下载
- 积分：1
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StepMotor_CurrentLoop
实现二项混合式步进电机的驱动，和步进电机的细分程序。(The driving of binomial hybrid stepper motor and the subdivision program of stepper motor are realized.)
- 2020-06-21 02:20:01下载
- 积分：1
