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MCU_V_PWM_16bit
单片机通过总线，将占空比和频率送到CPLD/FPGA中，并控制PWM输出.采用Verilog HDL语言编写。(Microcontroller by bus, the duty cycle and frequency sent to the CPLD/FPGA in, and control the PWM output. Using Verilog HDL language.)
- 2020-10-29 09:19:57下载
- 积分：1
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verilog hdl coding DDR sdram control for fpga
verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga
- 2022-03-23 21:20:26下载
- 积分：1
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基于EPM1270
基于EPM1270的EProm at24c02 驱动-Based on the EPM1270
- 2022-02-27 00:52:37下载
- 积分：1
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flashZ
FPGA控制m25p16flash芯片读写控制spi协议
可实现擦除写入读出功能(SPI protocol for read and write control of m25p16 flash chip controlled by FPGA
Erase Write-Read Function)
- 2018-12-19 16:10:59下载
- 积分：1
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异步串行接口电路及数据传输模块设计
设计要求1） 每帧数据供 10 位，其中 1位启动， 8位数据， 1位 停止。2） 波特率为： 9600 。3） 收发误码率
- 2023-09-07 19:10:03下载
- 积分：1
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hwref
spartan 3 hardware reference document xilinx
- 2009-05-22 19:10:33下载
- 积分：1
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本设计是针对LEON3 Altera Nios II startix2
This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the
- 2022-05-18 19:00:04下载
- 积分：1
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vedic_Code
vedic multiplication
- 2015-11-16 19:19:40下载
- 积分：1
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verilog
关于USB开发的verilog开发程序，非常的全面，学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)
- 2013-12-26 18:29:35下载
- 积分：1
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联邦滤波法lianbanglvbo
联邦滤波法，毕设时写的，可以和其他方法的做比较(Kalman filter, write the complete set up, and other methods to compare)
- 2020-12-01 18:49:26下载
- 积分：1
