-
利用扫描加记数程序实现百进制,适合VHDL的初学者使用.
利用扫描加记数程序实现百进制,适合VHDL的初学者使用.-increase in the use of scanning program in mind several hundred 229 and is suitable for beginners to use VHDL.
- 2022-03-21 06:59:03下载
- 积分：1
-
VHDL prepared by the FIR filter source for Embedded designers have a good role i...
VHDL语言编写的FIR滤波器源码
对于嵌入式设计者有很好的指导作用
-VHDL prepared by the FIR filter source for Embedded designers have a good role in guiding
- 2022-06-17 20:08:46下载
- 积分：1
-
altera DE1 SD_CARD带写入一个扇区功能的程序，已确认成功，下载直接运行就可以看效果...
altera DE1 SD_CARD带写入一个扇区功能的程序，已确认成功，下载直接运行就可以看效果-altera DE1 SD_CARD with a sector write function procedures, has confirmed the success of running can be downloaded directly watch the effect of
- 2022-04-16 19:05:08下载
- 积分：1
-
FSM
It is the FSM implemented in Xylinx 14.7 on FPGA
- 2015-09-28 15:50:09下载
- 积分：1
-
VHDL实现的超前进位加法器
VHDL实现的超前进位加法器-the VHDL-ahead Adder
- 2022-02-26 07:08:05下载
- 积分：1
-
基于FPGA的CPU核及其虚拟平台的设计与实现
基于FPGA的CPU核及其虚拟平台的设计与实现-FPGA-based CPU core and its virtual platform design and implementation of
- 2022-08-08 02:35:45下载
- 积分：1
-
mult_16
用verilog实现对三个16位数进行相加乘法器(Three 16-digit sum of the multiplier Verilog)
- 2021-01-03 10:28:55下载
- 积分：1
-
SRAM
进阶实验之SRAM测试，由verilog编写，可直接对sram进行存写(Advanced SRAM test experiments, written by the verilog, can be stored directly on the sram write)
- 2011-08-18 01:58:56下载
- 积分：1
-
fujieqi
在这里设计的是时分复用系统，就是要将三路8比特数据复用到同一信道上进行传输(Here is the design of time division multiplexing system, is to take the road three 8 bit data multiplexed onto the same channel for transmission)
- 2014-10-16 09:31:25下载
- 积分：1
-
xilinx CTC IPcore 误码率测试
xilinx CTC IPcore 误码率测试-xilinx CTC IPcore Bit Error Rate Test
- 2022-07-17 12:20:15下载
- 积分：1
