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基于VHDL的自动售货机实现,包含完整的源代码,锁脚文件以及下载文件
基于VHDL的自动售货机实现,包含完整的源代码,锁脚文件以及下载文件-VHDL-based vending machine realize that contains the complete source code, locking pin, as well as download files documents
- 2022-07-09 00:04:25下载
- 积分：1
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LS165
LS165移位寄存器的verilog语言编写(The writing of the Verilog language of LS165 shift register)
- 2020-11-22 22:59:34下载
- 积分：1
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car
基于Xilinx公司的ISE软件开发的智能循迹避障小车的源代码，用Verilog语言，传感器有红外传感器以及超声波传感器(Xilinx' s ISE-based software development intelligent car tracking avoidance source code, using Verilog language, the sensor has an infrared sensor and ultrasonic sensors)
- 2015-03-21 18:06:18下载
- 积分：1
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Altera QUARTUS 7.2的矩阵键盘电子琴完整工程（含源码），在EP2C20芯片上实现...
Altera QUARTUS 7.2的矩阵键盘电子琴完整工程（含源码），在EP2C20芯片上实现-Altera QUARTUS 7.2 Project of matrix keyboard electronic organ, implement on EP2C20 chip.
- 2022-02-01 23:23:04下载
- 积分：1
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VGA 测试程序，可显示彩色条纹，用vhdl语言编写，经过测试，运行稳定，带有注释！...
VGA 测试程序，可显示彩色条纹，用vhdl语言编写，经过测试，运行稳定，带有注释！-VGA test procedure can be displayed color stripes, using VHDL language, tested and stable operation with Notes!
- 2023-06-28 09:05:04下载
- 积分：1
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sdram_module3
能够实现16位的SDRAM的读写，没有仿真文件，只有SDRAM读写的源代码，用Verilog编写(can complete read or write sdram， only include Verilog code and no simulation files)
- 2013-11-25 12:43:11下载
- 积分：1
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zixiechengxu
用verilog编写的包含有与DSP通信，三电平svpwm实现的程序，(Written in verilog contains communicate with the DSP, three-level svpwm realize the procedures)
- 2021-04-18 15:28:51下载
- 积分：1
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SVPWM_method
给出了SVPWM算法的详细FPGA实现方法！(A detailed FPGA SVPWM algorithm to achieve the method!)
- 2017-04-05 13:43:14下载
- 积分：1
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Lab15_sw2reg
开关数据加载到寄存器并显示的设计与实现.3． 设计一个可以把4个开关的内容存储到一个4位寄存器的电路，并在最右边的7段显示管上显示这个寄存器中的十六进制数字。我们使用到去抖动模块clock_pulse， 用btn[0]作为输入；8位寄存器模块，用btn[1]作为加载信号；7段显示管上的显示模块x7segbc；分频模块clkdiv，用以产生模块clock_pulse和x7segbc的clk190时钟信号。(Design of switching data is loaded into the register and display the.3. design and implementation of a 4 switch content storage circuit to a 4 bit register, and in the 7 section of the most on the right shows the register in the sixteen decimal digital display tube. We used to go to the jitter module clock_pulse, with btn[0] as the input 8 bit register module, as the loading signal by btn[1] 7 segment display module on the x7segbc pipe frequency module clkdiv, clk190 clock signal for generating module clock_pulse and x7segbc.)
- 2014-03-30 09:50:48下载
- 积分：1
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prepared using VHDL stepper motor control methods. For your reference.
用VHDL编写的步进电机控制方法.供大家参考用.-prepared using VHDL stepper motor control methods. For your reference.
- 2022-06-16 01:54:04下载
- 积分：1
