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ExpectedBoardDetails1.txt
Use full for knowing board details while making projects on FPGA and matlab simulations
- 2013-11-20 17:47:58下载
- 积分：1
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(2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过
(2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through
- 2022-05-25 02:39:25下载
- 积分：1
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RScoder
基于FPGA的RS编码器设计，verilog hdl语言。(RS encoder FPGA-based design, verilog hdl language.)
- 2011-07-17 22:18:08下载
- 积分：1
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ps2接口的工程实现，顶层为原理图，便于理解
ps2接口的工程实现，顶层为原理图，便于理解-ps2 interface engineering implementation, the top-level schematic diagram for easy understanding of
- 2022-07-10 06:48:35下载
- 积分：1
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ds18b20
说明： ds18b20的Verilog程序，经测试验证可以使用。注意此版本为DALLS DS18B20而不是DS1820,注意加5K上拉电阻。(ds18b20 the Verilog process can be used to verify by testing. Note that this version rather than DALLS DS18B20 for DS1820, the attention of Canadian 5K pull-up resistor.)
- 2020-10-29 11:09:56下载
- 积分：1
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Lpfilter_20190503
说明： 环路滤波器是通信信号调制解调中最重要的一个部分，环路滤波器设计的好坏将直接影响到接收机的性能指标，二阶锁频辅助三阶锁相环路滤波器可以稳定跟踪具有加加速度的信号源，是现代通信中非常实用的技术，本文中详细编写了单载波信号产生模块、信道噪声模块、数字正交下变频模块、鉴频鉴相模块、环路滤波器模块，并包含了完整的testbench模块，对于初学者非常有用。(Loop filter is the most important part of communication signal modulation and demodulation. The design of loop filter will directly affect the performance index of receiver. The second-order frequency locking assisted third-order phase-locked loop filter can stably track the signal source with acceleration speed, which is a very practical technology in modern communication. In this paper, the single carrier signal generation module and channel noise are written in detail Sound module, digital orthogonal down conversion module, frequency and phase detection module, loop filter module, and contains a complete testbench module, which is very useful for beginners.)
- 2020-11-11 01:27:25下载
- 积分：1
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图像处理VHDL
XAPP928,可以参考学习.里面包含了色温调整、GAMMA调整以及空间抖动增强灰度算法，这３个基本是现在平板显示设备常用的图像预处理算法。
- 2022-02-28 13:41:00下载
- 积分：1
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des加密算法的verilog语言的实现
des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language
- 2023-09-07 20:45:02下载
- 积分：1
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ethernet_udp_ep4c_ok_final
用ALTERA的FPGA实现UDP通信源代码(FPGA UDP)
- 2015-04-27 01:15:36下载
- 积分：1
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TRY-1516-CSV0115--- SANGEETHA
说明： VHDL BASED DATA COMPRESSION
- 2019-01-01 16:37:53下载
- 积分：1
