-
systolic
实现QR_RLS算法,基于fpga
的非线性功放的dpd实现(realize QR_RLS)
- 2012-02-24 10:07:34下载
- 积分:1
-
Sdram_Control_4Port
使用verilog HDL写的sdram(SDR)的控制器源代码,具有很好的可移植性,试验的例子已经通过QuartusII 9.0编译通过,可以运行在cycloneII上(Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII)
- 2012-05-14 15:36:09下载
- 积分:1
-
FPGA-SRAM_Test
利用FPGA实现SDRAM的读写操作,通过硬件测试。(FPGA implementation using SDRAM to read and write operation, hardware testing.)
- 2011-08-03 22:52:25下载
- 积分:1
-
exp12
说明: 浙江大学计算机组成实验12指令扩展多周期CPU实现(The implementation of 12 instruction extended multi cycle CPU in Computer Composition Experiment of Zhejiang University)
- 2020-10-09 16:17:35下载
- 积分:1
-
拥有VGA彩色信号发生器Verilog ISE环境
自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment
- 2023-01-14 23:05:03下载
- 积分:1
-
bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools
32bits FIFO with synchronizer. pass the synthesis using Synopsys tools-bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools
- 2023-01-08 07:50:03下载
- 积分:1
-
sdram-source
SDR SDRAM 控制器的源代码 altera公司的(source code from altera)
- 2010-06-09 19:35:03下载
- 积分:1
-
fpga_dk_ps2_vga
ps2 vga interface in vhdl code
- 2011-11-08 11:09:35下载
- 积分:1
-
S03_基于ZYNQ的DMA与VDMA的应用开发
说明: VIVADO dma以及vdma 使用文档 基于ZYNQ 7020(vivado DMA&VDMA example text of zynq)
- 2020-06-17 11:40:02下载
- 积分:1
-
以太网控制器Verilog源码(含有MAC,MII接口)
以太网控制器Verilog源码(含有MAC,MII接口)(Ethernet controller Verilog source code (including MAC, MII interface))
- 2017-08-18 10:32:27下载
- 积分:1