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Encoder_SSI_Veryilog
说明： 本文详细描述了SSI协议的通讯格式、原理及应用电路,并采用verilog语言实现了SSI通讯协议.设计实用电路并实现了与绝对值编码器的通讯(SSI protocol described in detail the communication format, principle and application circuit, and use verilog language of the SSI protocol. Practical circuit design and implementation of the communication with the absolute encoder)
- 2020-12-28 20:59:02下载
- 积分：1
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jiaotongdeng
基于CPLD的交通灯控制，完成交通灯的功能，校错能力(CPLD-based control of traffic lights, traffic lights to complete the function, the school was wrong capacity)
- 2010-10-08 23:12:11下载
- 积分：1
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16QAM
基于FPGA 16QAM解调verilog代码，(16QAMdemoluator veriliog)
- 2021-02-23 23:49:39下载
- 积分：1
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described dds direct digital frequency synthesis of the basic tenets addition to...
讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output
- 2022-07-08 20:48:31下载
- 积分：1
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LDPC.DIFFERENT-CODE-LONGTH
LDPC码不同码长对比。码率选择1/2.码长分别为256，512，1024.(LDPC codes of different code length contrast. Bitrate select 1/2 yards long were 256,512,1024.)
- 2012-11-22 10:53:04下载
- 积分：1
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CH2CH1VHDL 数字电路参考书所有程序4
CH2CH1VHDL 数字电路参考书所有程序4-CH2CH1VHDL digital circuit reference all proceedings 4
- 2022-07-15 17:40:45下载
- 积分：1
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Crack_QII_13.1_Windows
采用骏龙科技这个13.1新版本破解器.对于已经用了老版本破解器的网友，请把bin和bin64下的sys_cpt.dll删除，然后把sys_cpt.dll.bak名字改成sys_cpt.dll，也就是先恢复正版，然后用这个破解器破解。注意老的license文件也要删除，改用这个新版本破解器附带的license(Cytech Technology 13.1 using the new version of this cracker. Has been used for the old version cracker users, please sys_cpt.dll bin and bin64 under Delete, and then changed the name of the sys_cpt.dll.bak sys_cpt.dll, which is first restore genuine, then use this cracker to crack. Note that the old license file should be deleted in favor of this new version of the license that came with crack)
- 2021-03-04 09:59:32下载
- 积分：1
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基于FPGA的数字频率计设计
使用飓风开发板，完成了100M，频率计设计，并可在数码管显示
- 2022-02-25 11:23:58下载
- 积分：1
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FPGA2-DSP2-EDMA
例程是基于quartus的，FPGA通过EMIF给DSP发送数据，里面包含了一个简单的状态机和一个基于IP核的fifo，适合初学者(Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners)
- 2020-12-04 16:09:24下载
- 积分：1
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JTAG
边界扫描技术相关资料，含各个模块的介绍。很有参考价值。(JTAG TAG CONTROLLER)
- 2016-02-24 19:10:03下载
- 积分：1
