登录
首页 » VHDL » fft in dspbuilder under VHDL source code and test incentives document matl ab mo...

fft in dspbuilder under VHDL source code and test incentives document matl ab mo...

于 2022-03-14 发布 文件大小:7.63 kB
0 212
下载积分: 2 下载次数: 1

代码说明:

fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 004
    51单片机的下载器PCB图,可以用于at89cXX和at89c0xx系列的单片机的程序烧录,简单好用!使用proteus画的板。(51 MCU PCB map downloader, can be used at89cXX and procedures for microcontroller series at89c0xx burning, easy to use! Drawing board with proteus.)
    2011-10-26 11:03:40下载
    积分:1
  • vga_interface_requiring_core_regeneration
    vga interface with text rom. font size 80x40. core need core regeneration.
    2013-05-19 02:09:10下载
    积分:1
  • 基于MATLAB模型设计的FPGA开发与实现
    说明:  MATLAB的SIMULINK和FPGA联合设计滤波器等,摆脱了传统的代码设计。(MATLAB's SIMULINK and FPGA jointly design filters and so on, and get rid of the traditional code design.)
    2020-10-23 16:07:23下载
    积分:1
  • Signed-Arithmetic-in-Verilog-2001
    有符号数的完整讲义和例子Verilog 2001(Signed Arithmetic in Verilog 2001, paper with examples)
    2011-01-18 17:15:09下载
    积分:1
  • VHDL电子抢答器的实现。有多个文件,主控件是用图行实现。其余各功能模块用VHDL实现...
    VHDL电子抢答器的实现。有多个文件,主控件是用图行实现。其余各功能模块用VHDL实现-VHDL electronic Responder realized. A number of documents, the main controls are using maps the bank. The remaining modules using VHDL
    2022-03-14 00:36:42下载
    积分:1
  • 实现dds功能,利用quartus软件, 子模块包括加法器,锁相环,date...
    实现dds功能,利用quartus软件, 子模块包括加法器,锁相环,date-rom 利用原图将各模块综合,利用ps2键盘控制频率及相位。-Dds realize functions, using Quartus software, sub-modules including the adder, phase-locked loop, date-rom image to the module using integrated, using ps2 keyboard to control the frequency and phase.
    2022-01-26 04:52:55下载
    积分:1
  • HASH
    hash加速器的verilog实现,也用于fpga或asic(hash verilog rtl )
    2015-01-29 18:48:13下载
    积分:1
  • du to fpga 4*4 keyscan verilog
    基于fpga的4*4键盘扫描verilog程序-du to fpga 4*4 keyscan verilog
    2022-01-25 20:49:28下载
    积分:1
  • FPGA realization of the LCD interface, VHDL programming, FPGA chips for Altera
    FPGA实现的LCD接口,VHDL编程,FPGA芯片为ALtera公司的EP2c35-FPGA realization of the LCD interface, VHDL programming, FPGA chips for Altera
    2022-09-14 14:30:09下载
    积分:1
  • AHDL
    AHDL语言介绍,很详细的介绍AHDL语言介绍,很详细的介绍(AHDL language introduction, a detailed explanation)
    2009-11-17 15:27:59下载
    积分:1
  • 696516资源总数
  • 106783会员总数
  • 25今日下载