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flash
fpga Verilog 控制读写flash (fpga Verilog flash )
- 2015-06-23 14:45:44下载
- 积分：1
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labview-filter
数字滤波器包含IIR数字滤波器和FIR数字滤波器。本设计的工作主要是Labview软件部分，包括信号生成模块、滤波模块、显示模块的设计(IIR digital filter comprises a digital filter and FIR digital filters. The design work is mainly Labview software parts, including signal generation module, filter module, display module design)
- 2014-06-05 22:22:37下载
- 积分：1
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Verilog--image-sample
基于Verilog的图像采集、处理和存储程序，初学者参考，高手绕道。(Verilog-based image acquisition, processing and storage procedures, beginners reference, master bypass.)
- 2021-04-16 11:48:54下载
- 积分：1
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FIRfilterverilogHDL
FIR滤波器的verilog HDL代码示例，以16阶为例(Verilog HDL code for fir filter)
- 2015-07-08 17:05:38下载
- 积分：1
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dgnszsz
多功能数字钟，在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)
- 2013-09-20 10:20:31下载
- 积分：1
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vivado 从此开始配套资料
说明： vivado入门使用介绍，初学者入门学习(vivado Instructional pdf)
- 2020-07-04 18:00:01下载
- 积分：1
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dianzhen
fpga实验板上16*16点阵显示汉字的程序-翻译结果fpga实验板上16*16点阵显示汉字的程序(Experimental fpga board 16* 16 dot matrix display Chinese program- translation results fpga experimental board 16* 16 dot matrix display Chinese characters in the program)
- 2013-12-24 16:28:00下载
- 积分：1
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MP3
MP3解码的ASIC全部过程，包换含c和vhdl代码，样例。(MP3 decoding ASIC whole process, shifting with c and vhdl code, sample.)
- 2021-01-02 22:48:57下载
- 积分：1
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HDMI接口编解码传输模块ASIC设计_刘文杰
? 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
? 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。
? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
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cpu_easy
说明： ADD MOV MOVi SUB四指令cpu设计，qutartus，(Design of four-instruction CPU)
- 2019-05-13 11:44:49下载
- 积分：1
